SM59R16A5/SM59R09A5/SM59R05A5
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
can be disabled / enabled by the WDTE bit.
0: Disable WDT.
1: Enable WDT.
The WDTE bit is not used if WDTEN is "1". That is, if the WDTEN bit is "1", WDT is
always disabled no matter what the WDTE bit status is. The WDTE bit can be read and
written.
WDTM [3:0]: WDT clock source divider bit. Please see table 10.1 to reference the WDT time-out
period.
Mnemonic: WDTK
Address: B7h
7
6
5
4
3
2
1
0
Reset
00h
WDTK[7:0]
WDTK: Watchdog timer refresh key.
A programmer must write 0x55 into WDTK register, and then the watchdog
timer will be cleared to zero.
For example, if enable WDT and select time-out reset period is 262.14ms.
First, programming the WDTEN to “0”.
Secondly,
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
MOV WDTC, #28h
; enable WDTC write attribute.
; Set WDTM [3:0] = 1000b. Set WDTE =1 to enable WDT
; function.
.
.
.
MOV WDTK, #55h
; Clear WDT timer to 0.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M047 50 Ver.G SM59R16A5 01/2014
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
