SM59R16A5/SM59R09A5/SM59R05A5
8-Bit Micro-controller
64KB/36KB/20KB with ISP Flash
& 2KB RAM embedded
to count from the beginning. The watchdog timer must be refreshed regularly to prevent reset request signal from
becoming active.
When Watchdog timer is overflow, the WDTF flag will set to one and automatically reset MCU. The WDTF flag can be
clear by software or external reset or power on reset.
Clear
WDTF = 0
Power on reset
External reset
Software write “0”
250KHz RC
oscillator
WDTF
Set WDTF = 1
WDT time-out reset
WDTCLK
1
TAKEY
(55, AA, 5A)
WDT
Counter
2WDTM
WDTM[3:0]
Enable/Disable
WDT
Refresh
WDT Counter
WDTC
Enable WDTC
write attribute
WDTK
(0x55)
WDTEN
Fig. 10-1: Watchdog timer block diagram
Mnemonic
Description
Direct
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
Watchdog Timer
Time Access Key
register
Watchdog timer
control register
Watchdog timer
refresh key
TAKEY
WDTC
WDTK
F7h
B6h
B7h
TAKEY [7:0]
-
00H
04H
00H
WDTF
-
WDTE
WDTM [3:0]
WDTK[7:0]
Mnemonic: TAKEY
Address: F7h
7
6
5
4
3
2
1
0
Reset
00H
TAKEY [7:0]
Watchdog timer control register (WDTC) is read-only by default; software must write three specific
values 55h, AAh and 5Ah sequentially to the TAKEY register to enable the WDTC write attribute. That is:
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
Mnemonic: WDTC
Address: B6h
7
6
-
5
4
-
3
2
1
0
Reset
04H
WDTF
WDTE
WDTM [3:0]
WDTF: Watchdog timer reset flag.
When MCU is reset by watchdog, WDTF flag will be set to one by hardware. This flag
clear by software or external reset or power on reset.
WDTE: Control bit used to enable Watchdog timer.
The WDTE bit can be used only if WDTEN is "0". If the WDTEN bit is "0", then WDT
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M047 49 Ver.G SM59R16A5 01/2014
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
