SM59A16U1
8-Bit Micro-controller
64KB with ISP Flash
& 6K+256B RAM embedded
Mnemonic: PCON
7
6
SMOD MDUF
5
4
-
3
2
1
STOP
Address: 87h
0
Reset
IDLE
40h
MDUF: MDU finish flag.
When MDU is finished, the MDUF will be set by hardware and the bit will clear
by hardware at next calculation.
The following table gives the execution time in every mathematical operation.
Table 6-3: MDU execution times
Number of Tclk
17 clock cycles
9 clock cycles
11 clock cycles
Min. 3 clock cycles, Max. 18 clock cycles
Min. 4 clock cycles, Max. 19 clock cycles
Operation
Division 32bit/16bit
Division 16bit/16bit
Multiplication
Shift
Normalize
6.2.3
Third phase: reading the result from the MDx registers.
Read out sequence of the first MDx registers is not critical but the last read (from MD5 - division and MD3 -
multiplication, shift and normalizing) determines the end of a whole calculation (end of phase three).
Operation
First read
Last read
Table 6-4: MDU registers read sequence
32Bit/16Bit
16Bit/16Bit
16Bit x 16Bit
MD0 Quotient Low
MD0 Quotient Low
MD0 Product Low
MD1 Quotient
MD1 Quotient High
MD1 Product
MD2 Quotient
MD2 Product
MD3 Quotient High
MD4 Remainder L
MD4 Remainder Low
MD5 Remainder H
MD5 Remainder High
MD3 Product High
shift/normalizing
MD0 LSB
MD1
MD2
MD3 MSB
Here the operation of normalization and shift will be explained more. In normalization, all reading zeroes in registers
MD0 to MD3 are removed by shift left. The whole operation is completed when the MSB (most significant bit) of MD3
register contains a ‟1‟. After normalizing, bits ARCON.4 (MSB) to ARCON.0 (LSB) contain the number of shift left
operations. As for shift, SLR bit (ARCON.5) has to contain the shift direction, and ARCON.4 to ARCON.0 represent
the shift count (which must not be 0). During shift, zeroes come into the left or right end of the registers MD0 or MD3,
respectively.
6.3
Normalizing
All reading zeroes of integers variables in registers MD0 to MD3 are removed by shift left operations. The whole
operation is completed when the MSB (most significant bit) of MD3 register contains a ‟1‟. After normalizing, bits
ARCON.4 (MSB) to ARCON.0 (LSB) contain the number of shift left operations, which were done.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M071
Ver A
SM59A16U1
04/12/2013
- 44 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
