SM59A16U1
8-Bit Micro-controller
64KB with ISP Flash
& 6K+256B RAM embedded
TLx overflows, a value from THx is copied to
TLx.
1
1
Mode3 If Timer 1 M1 and M0 bits are set to 1, Timer 1
stops. If Timer 0 M1 and M0 bits are set to 1,
Timer 0 acts as two independent 8 bit timers /
counters.
7.2
Timer/Counter Control Register( TCON )
Mnemonic: TCON
Address: 88h
7
TF1
6
TR1
5
TF0
4
TR0
3
IE1
2
IT1
1
IE0
0
IT0
Reset
00h
TF1: Timer 1 overflow flag set by hardware when Timer 1 overflows. This flag can
be cleared by software and is automatically cleared when interrupt is
processed.
TR1: Timer 1 Run control bit. If cleared, Timer 1 stops.
TF0: Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can
be cleared by software and is automatically cleared when interrupt is
processed.
TR0: Timer 0 Run control bit. If cleared, Timer 0 stops.
IE1: Interrupt 1 edge flag. Set by hardware, when falling edge on external pin
INT1 is observed. Cleared when interrupt is processed.
IT1: Interrupt 1 type control bit. Selects falling edge or low level on input pin to
cause interrupt. IT1=1, interrupt 1 select falling edge trigger. IT1=0, interrupt1
select low level trigger.
IE0: Interrupt 0 edge flag. Set by hardware, when falling edge on external pin
INT0 is observed. Cleared when interrupt is processed.
IT0: Interrupt 0 type control bit. Selects falling edge or low level on input pin to
cause interrupt. IT0=1, interrupt 0 select falling edge trigger. IT0=0, interrupt
0 select low level trigger.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M071 Ver A SM59A16U1 04/12/2013
- 47 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
