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SM59A16U1U48VP 参数 Datasheet PDF下载

SM59A16U1U48VP图片预览
型号: SM59A16U1U48VP
PDF下载: 下载PDF文件 查看货源
内容描述: SM59A16U1 8位微控制器 64KB具有ISP闪存 & 6K + 256B RAM嵌入式 [SM59A16U1 8-Bit Micro-controller 64KB with ISP Flash & 6K+256B RAM embedded]
分类和应用: 闪存微控制器
文件页数/大小: 146 页 / 4372 K
品牌: SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
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SM59A16U1  
8-Bit Micro-controller  
64KB with ISP Flash  
& 6K+256B RAM embedded  
5. GPIO  
The SM59A16U1 has four I/O ports: Port 0, Port 1, Port 2, Port 3 and Port 4. Ports 0, 1, 2, 3, are 8-bit ports and Port 4  
is a 6-bit port. These are: quasi-bidirectional (standard 8051 port outputs), push-pull, open drain, and input-only. Two  
configuration registers for each port select the output type for each port pin. All I/O port pins on the SM59A16U1 may  
be configured by software to one of four types on a pin-by-pin basis, shown as below:  
Mnemonic  
Description  
Dir.  
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0  
RST  
I/O port function register  
P0M0  
P0M1  
P1M0  
P1M1  
P2M0  
P2M1  
P3M0  
P3M1  
Port 0 output mode 0  
Port 0 output mode 1  
Port 1 output mode 0  
Port 1 output mode 1  
Port 2 output mode 0  
Port 2 output mode 1  
Port 3 output mode 0  
Port 3 output mode 1  
D2h  
D3h  
D4h  
D5h  
D6h  
D7h  
DAh  
DBh  
P0M0 [7:0]  
P0M1[7:0]  
P1M0[7:0]  
P1M1[7:0]  
P2M0[7:0]  
P2M1[7:0]  
P3M0[7:0]  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
P3M1[7:0]  
P4M P4M P4M P4M P4M P4M  
P4M0  
P4M1  
Port 4 output mode 0  
Port 4 output mode 1  
DCh  
DDh  
-
-
-
-
00H  
00H  
0.6  
P4M P4M P4M P4M P4M P4M  
1.6 1.5 1.4 1.3 1.2 1.1  
0.5  
0.4  
0.3  
0.2  
0.1  
Note: P0 is input only, when reset assert (even P1M0 reset value is 00H).  
PxM1.y  
PxM0.y  
Port output mode  
0
0
1
1
0
1
0
1
Quasi-bidirectional (standard 8051 port outputs) (pull-up)  
Push-pull  
Input only (high-impedance)  
Open drain  
The OCI_SCLALE and OCI_SDA can be define as P4.4P4.5 and P4.6 by writer or ISP。  
For general-purpose applications, every pin can be assigned to either high or low independently as given below:  
Mnemonic  
Description  
Dir.  
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0  
Ports  
RST  
Port 0  
Port 1  
Port 2  
Port 3  
Port 4  
Port 0  
Port 1  
Port 2  
Port 3  
Port 4  
80h  
90h  
A0h  
B0h  
E8h  
P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0  
P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0  
P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0  
P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0  
FFh  
FFh  
FFh  
FFh  
FFh  
-
P4.6 P4.5 P4.4 P4.3 P4.2 P4.1  
-
5.1  
P0 ( Port 0 Register )  
Mnemonic: P0  
Address: 80h  
7
P0.7  
6
P0.6  
5
P0.5  
4
P0.4  
3
P0.3  
2
P0.2  
1
P0.1  
0
P0.0  
Reset  
FFh  
P0.7~ 0: Port0 [7] ~ Port0 [0]  
P1 ( Port 1 Register)  
Mnemonic: P1  
Specifications subject to change without notice contact your sales representatives for the most recent information.  
5.2  
Address: 90h  
ISSFD-M071 Ver A SM59A16U1 04/12/2013  
- 40 -  
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