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SM5964AL25 参数 Datasheet PDF下载

SM5964AL25图片预览
型号: SM5964AL25
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器,具有64KB ISP功能的Flash和TWSI与PWM和1KB RAM的嵌入式 [8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded]
分类和应用: 微控制器
文件页数/大小: 30 页 / 886 K
品牌: SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
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SyncMOS Technologies International, Inc.  
SM5964A  
8-Bit Micro-controller  
With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded  
Internal Data memory  
The Data memory of SM5964A consists of 1024 bytes internal data memory (256 bytes standard RAM and 768 bytes  
AUX-RAM). The AUX-RAM is enable by SCONF.1 ($BF.1), and read/write by MOVX  
Internal RAM Control Register (RCON, $85)  
Bit7  
Bit6  
Bit5  
Bit4  
Bit3  
Bit2  
Bit1  
Bit0  
RAMS1  
RAMS0  
SM5964A has 768 byte on-chip RAM which can be accessed by external memory addressing method only. (By  
instruction MOVX). The address space of instruction MOVX @Rn is determined by bit 1 and bit 0 (RAMS1, RAMS0) of  
RCON. The default setting of RAMS1, RAMS0 bits is 00 (page0).  
Pulse Width Modulation (PWM)  
The PWM output pins are P1.2 and P1.3.  
The PWM clock is {FOSC/ (2xDivider)}, the PWM output frequency is {(PWM clock)/32} at 5 bits resolution and  
{(PWM clock)/256} at 8 bits resolution.  
The PWM SFR has shown as below:  
PWMC [0:1] ($D3H and $D4H)  
Bit7  
Bit6  
Bit5  
Bit4  
Bit3  
Bit2  
PBS  
Bit1  
PFS1  
Bit0  
PFS0  
PBS: when set, the PWM is 5 bits resolution.  
PFS [1:0]: The PWM clock divider select.  
PFS1  
PFS0  
PWM clock divider select  
0
0
1
1
0
1
0
1
2
4
8
16  
PWMD [0:1] ($B3H and $B4H)  
Bit7  
PWMD.7  
Bit6  
PWMD.6  
Bit5  
PWMD.5  
Bit4  
PWMD.4  
Bit3  
PWMD.3  
Bit2  
PWMD.2  
Bit1  
PWMD.1  
Bit0  
PWMD.0  
Two-Wire Series Interface (TWSI)  
The TWSI module uses the SCL (clock) and the SDA (data) line to communicate with external TWSI interface between  
other TWSI parts. The speed can up to 400K bps (max.) by software setting the TWSIFS [2:0].  
The TWSI module used SFR shown as below  
TWSI Status Register:  
TWSIS ($C0H)  
Bit7  
Bit6  
Bit5  
Bit4  
Bit3  
Bit2  
Bit1  
Bit0  
RXIF  
TXIF  
TFIF  
NAKIF  
RXAK  
MASTER  
TXAK  
RXIF: The data Receive Interrupt Flag (RXIF) is set after the TWSIRxD (TWSI Receive Data Buffer) is loaded with a  
newly receive data.  
TXIF: The data Transmit Interrupt Flag (TXIF) is set when the data of the TWSITxD (TWSI Transmit Data Buffer) is  
downloaded to the shift register or the TWSIA is downloaded to the shift register at Master Transmit mode.  
TFIF: The Transmit Fail Interrupt Flag is set when the data transmit fail.  
Specifications subject to change without notice contact your sales representatives for the most recent information.  
Ver 2.3 SM5964A 10/2006  
20  
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