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SM5964AL25 参数 Datasheet PDF下载

SM5964AL25图片预览
型号: SM5964AL25
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器,具有64KB ISP功能的Flash和TWSI与PWM和1KB RAM的嵌入式 [8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded]
分类和应用: 微控制器
文件页数/大小: 30 页 / 886 K
品牌: SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
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SyncMOS Technologies International, Inc.  
SM5964A  
8-Bit Micro-controller  
With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded  
Addressing Mode  
Notes on instruction set and address modes:  
Rn  
Register R7-R0 of the currently selected register bank.  
direct  
8-bits internal data location’s address. This could be internal DATA RAM location (0-127) or a SFR  
[i.e., I/O port, control register, status register, etc. (128-255)]  
@Ri  
#data  
8-bits RAM location addressed indirectly through register R1 or R0 of the actual register bank  
8-bits constant included in the instruction  
#data16  
addr11  
16-bits constant included in the instruction  
11-bits destination address. Used by ACALL and AJMP. The branch can be anywhere within the same 2  
K bytes page of program memory as the first byte of the following instruction.  
Signed (2’s complement) 8-bits offset byte. Used by SJMP and all conditional jumps. Range is -128 to  
+127 bytes relative to first byte of the following instruction.  
rel  
bit  
Direct addressed bit in internal data RAM or SFR  
Table 4: A Summary of the instruction set  
Mnemonic  
OPERATION  
BYTE  
CYCLE  
Arithmetic Instructions  
ADD  
ADD  
ADD  
ADD  
ADDC  
ADDC  
A,Rn  
A = A + Rn  
1
2
1
2
1
2
1
1
1
1
1
1
A,direct  
A,@Ri  
A,#data  
A,Rn  
A = A + direct  
A = A + <@Ri>  
A = A + #data  
A = A + Rn + C  
A = A + direct + C  
A,direct  
ADDC  
ADDC  
SUBB  
A,@Ri  
A,#data  
A,Rn  
A = A + @Ri + C  
A = A + #data + C  
A = A Rn C  
1
2
1
1
1
1
SUBB  
SUBB  
SUBB  
A,direct  
A,@Ri  
A,#data  
2
1
2
1
1
1
A = A direct C  
A = A <@Ri> C  
A = A#data C  
A = A + 1  
Rn = Rn + 1  
direct = direct + 1  
<@Ri> = <@Ri> + 1  
A = A 1  
INC  
INC  
INC  
INC  
DEC  
A
Rn  
direct  
@Ri  
A
1
1
2
1
1
1
1
1
1
1
DEC  
DEC  
DEC  
INC  
Rn  
1
2
1
1
1
1
1
1
1
2
4
4
Rn = Rn 1  
direct  
@Ri  
DPTR  
AB  
direct = direct 1  
<@Ri> = <@Ri> 1  
DPTR = DPTR 1  
B:A = A × B  
MUL  
DIV  
AB  
A = INT (A/B)  
B = MOD (A/B)  
DA  
A
Decimal adjust ACC  
1
1
Logical Instructions  
A,Rn  
ANL  
ANL  
ANL  
ANL  
ANL  
ANL  
ORL  
ORL  
ORL  
ORL  
ORL  
ORL  
XRL  
XRL  
XRL  
XRL  
XRL  
XRL  
CLR  
A .AND. Rn  
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
A,direct  
A,@Ri  
A,#data  
direct,A  
direct,#data  
A,Rn  
A,direct  
A,@Ri  
A,#data  
direct,A  
direct,#data  
A,Rn  
A,direct  
A,@Ri  
A,#data  
direct,A  
direct,#data  
A
A .AND. direct  
A .AND. <@Ri>  
A .AND. #data  
direct .AND. A  
direct .AND. #data  
A .OR. Rn  
A .OR. direct  
A .OR. <@Ri>  
A .OR. #data  
direct .OR. A  
direct .OR. #data  
A .XOR. Rn  
A .XOR. direct  
A .XOR. <@Ri>  
A .XOR. #data  
direct .XOR. A  
direct .XOR. #data  
A = 0  
Specifications subject to change without notice contact your sales representatives for the most recent information.  
Ver 2.3 SM5964A 10/2006  
17  
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