SyncMOS Technologies International, Inc.
SM5964A
8-Bit Micro-controller
With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded
mode.
TWSIRXD ( $C5)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TWSIRxD.7 TWSIRxD.6 TWSIRxD.5 TWSIRxD.4 TWSIRxD.3 TWSIRxD.2 TWSIRxD.1 TWSIRxD.0
The TWSI Receive Data Buffer (TWSIRxD) contains the last received data when the MATCH flag is one or the calling
address from master when the MATCH flag is zero. The TWSIRxD register will be updated after a data byte is received
and the previous received data had been read out, otherwise the TWSI module will pull down to SCL line to inhabit the
next data transfer. It is a read-only register. The read operation of this register will clear the RXIF flag. After the RXIF
flag is cleared, the register can load the received data again and set the RXIF flag to generate interrupt request for reading
the newly received data.
In-System Programming (ISP)
The SM5964A can generator flash control signal by internal hardware circuit. That only need to put the ISP service code
into ISP code area (4 Kbytes and divided by 8 zones)
The area is set by lock-bit (N), the lock-bit number and ISP code area relation ship shown as below:
Lock-bit number
ISP code area
1
2
3
4
5
6
7
8
512 bytes (from $FE00h to $FFFF)
1K bytes (from $FC00H to $FFFF)
1.5 K bytes (from $FA00H to $FFFF)
2 K bytes (from $F800H to $FFFF)
2.5 K bytes (from $F600H to $FFFF)
3 K bytes (from $F400H to $FFFF)
3.5 K bytes (from $F200H to $FFFF)
4 K bytes (from $F000H to $FFFF)
There are three ways to into ISP code area:
1. Blank reset: Hardware reset with first flash address blank ($0000H = #FFH).
2. Execute the “LJMP” instruction.
3. By hardware setting:
P2.6
P2.7
RST
10ms
10ms
10ms
10ms
Or
P4.3
RST
The ISP register:
Specifications subject to change without notice contact your sales representatives for the most recent information.
Ver 2.3 SM5964A 10/2006
22
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
