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SM39A16M1U32 参数 Datasheet PDF下载

SM39A16M1U32图片预览
型号: SM39A16M1U32
PDF下载: 下载PDF文件 查看货源
内容描述: SM39A16M1\n8位微控制器\n16KB具有ISP功能的Flash\n& 1K + 256B RAM的嵌入式 [SM39A16M1 8-Bit Micro-controller 16KB with ISP Flash & 1K+256B RAM embedded]
分类和应用: 微控制器
文件页数/大小: 106 页 / 1520 K
品牌: SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
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SM39A16M1  
8-Bit Micro-controller  
16KB with ISP Flash  
& 1K+256B RAM embedded  
14. IIC function  
The IIC module uses the SCL (clock) and the SDA (data) line to communicate with external IIC interface. Its speed can  
be selected to 400Kbps (maximum) by software setting the IICBR [2:0] control bit. The IIC module provided 2 interrupts  
(RXIF, TXIF). It will generate START, repeated START and STOP signals automatically in master mode and can  
detects START, repeated START and STOP signals in slave mode. The maximum communication length and the  
number of devices that can be connected are limited by a maximum bus capacitance of 400pF.  
The interrupt vector is 6Bh.  
Mnemonic  
Description  
IIC control  
Dir.  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
RST  
IIC function  
AB_E  
N
IICCTL  
IICS  
F9h  
F8h  
IICEN  
-
MSS  
MPIF  
MAS  
LAIF  
BF_EN  
TXIF  
IICBR[2:0]  
TXAK  
04H  
00H  
register  
RW or  
BB  
IIC status register  
RXIF  
RXAK  
MATC  
H1or  
RW1  
MATC  
H2 or  
RW2  
IIC Address 1  
register  
IICA1  
IICA2  
FAh  
FBh  
IICA1[7:1]  
A0H  
60H  
IIC Address 2  
register  
IICA2[7:1]  
IIC Read/Write  
register  
IIC Enaable Bus  
Transaction  
IICRWD  
IICEBT  
FCh  
FDh  
IICRWD[7:0]  
00H  
00H  
FU_EN  
-
-
-
-
-
-
Mnemonic: IICCTL  
Address: F9h  
7
6
MSS  
5
MAS  
4
3
2
1
0
Reset  
04h  
IICEN  
AB_EN  
BF_EN  
IICBR[2:0]  
IICEN: Enable IIC module  
IICEN = 1 is Enable  
IICEN = 0 is Disable.  
MSS: Master or slave mode select.  
MSS = 1 is master mode.  
MSS = 0 is slave mode.  
*The software must set this bit before setting others register.  
MAS: Master address select (master mode only)  
MAS = 0 is to use IICA1.  
MAS = 1 is to use IICA2.  
AB_EN: Arbitration lost enable bit. (Master mode only)  
If set AB_EN bit, the hardware will check arbitration lost. Once arbitration lost occurred,  
hardware will return to IDLE state. If this bit is cleared, hardware will not care arbitration lost  
condition. Set this bit when multi-master and slave connection. Clear this bit when single  
master to single slave.  
BF_EN: Bus busy enable bit. (Master mode only)  
If set BF_EN bit, hardware will not generate a start condition to bus until BF=0. Clear this bit  
Specifications subject to change without notice contact your sales representatives for the most recent information.  
ISSFD-M069 Ver C SM39A16M1 7/31/2013  
- 79 -  
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