HV582
Functional Block Diagram
VDD
GND
DR
VPP
inA
D1
16 bit
shirt
register
LD1
D91
D2
DR
DG
HVout1
outA
Level
Xlator
Decoder
inA
16 bit
shirt
register
D92
D3
DG
DB
outA
HVGND
inA
16 bit
shirt
register
D93
D4
DB
DR
outA
96 bit
latch
inB
16 bit
shirt
register
D94
D5
DR
outB
DG
inB
16 bit
shirt
VPP
register
D95
D6
DG
DB
outB
inB
16 bit
shirt
register
HVout96
Level
Xlator
Decoder
CLK
DB
D96
LD96
outB
LE
POL
OLB
OHB
OE
HVGND
Function Table
Input
OE
Outputs
HV Outputs
Function
Shift Reg
Data
Out
Data CLK
LE
POL
OLB OHB
1
2...16
*…*
*…*
*…*
*…*
1
2...6
All low
All high
X
X
X
X
X
X
X
X
X
L
H
H
L
X
X
X
H
L
L
H
X
H
H
X
L
*
L
L…L
*
*
*
*
*
*
*
*
H
Z
H…H
Z…Z
*…* (b)
*…*
Outputs Hi-Z
Invert mode
Load S/R
X
X
H
H
X
H
H
*
H or L
L
H or L *…*
*
*
X
X
X
H
L
H
H
*
*…*
*…*
*
Store Data
in latches
X
L
H
H
H
H
L
L
H
H
H
H
H
H
*
*…*
*…*
*…*
*
*…* (b)
*…*
*
*
*
H
H
L
H
L
Transparent
Mode
H
H *…*
DIR is direction control: L shifts in CCW direction, QN❑QN-1; H shifts in CW direction, QN❑QN+1
Notes:
H = high level, L = low level, X = irrelevant, = low-to-high transition, (b) indicates inversion
* = dependent on previous stage’s state before the last CLK or last LE high.
5