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HV312 参数 Datasheet PDF下载

HV312图片预览
型号: HV312
PDF下载: 下载PDF文件 查看货源
内容描述: 测序热插拔控制器 [Sequencing Hotswap Controllers]
分类和应用: 控制器
文件页数/大小: 10 页 / 576 K
品牌: SUPERTEX [ Supertex, Inc ]
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Power Good Outputs (Referenced to VEE pin)  
VPWRGD-x(hi) Power Good Pin Breakdown Voltage  
VPWRGD-x(lo) Power Good Pin Output Low Voltage  
90  
V
V
µA  
PWRGD-x = HI Z  
IPWRGD = 1mA, PWRGD-x = LOW  
VPWRGD = 90V, PWRGD-x = HI Z  
0.5  
<1.0  
0.8  
10  
IPWRGD-x(lk)  
Maximum Leakage Current  
Dynamic Characteristics  
tGATEHLOV  
tGATEHLUV  
OV Comparator Transition  
UV Comparator Transition  
500  
500  
ns  
ns  
Note 1: This timing depends on the threshold voltage of the external N-Channel MOSFET. The higher its threshold is, the longer this timing.  
Note 2: This voltage depends on the characteristics of the external N-Channel MOSFET. Vto = 3V for an IRF530.  
*IRF530 is a registered trademark of International Rectifier.  
Pinout  
Pin Description  
PWRGD-D – This Power Good Output Pin is held inactive on initial  
power application and goes active a programmed time delay after  
PWRGD-C goes active.  
PWRGD-D (HV302)  
1
2
3
14  
13  
12  
11  
10  
9
________  
VDD  
TD  
PWRGD-D (HV312)  
PWRGD-C – This Power Good Output Pin is held inactive on initial  
power application and goes active a programmed time delay after  
PWRGD-B goes active.  
PWRGD-C (HV302)  
________  
PWRGD-C (HV312)  
PWRGD-B – This Power Good Output Pin is held inactive on initial  
power application and goes active a programmed time delay after  
PWRGD-A goes active.  
PWRGD-B (HV302)  
________  
TC  
PWRGD-B (HV312)  
PWRGD-A (HV302)  
________  
PWRGD-A – This Power Good Output Pin is held inactive on initial  
power application and goes active when the external MOSFET is  
fully turned on.  
4
TB  
PWRGD-A (HV312)  
OV – This Over Voltage (OV) sense pin, when raised above its  
high threshold will immediately cause the GATE pin to be pulled  
low. The GATE pin will remain low until the voltage on this pin falls  
below the low threshold limit, initiating a new start-up cycle.  
OV  
5
6
7
RAMP  
GATE  
SENSE  
UV  
UV – This Under Voltage (UV) sense pin, when below its low  
threshold limit will immediately cause the GATE pin to be pulled  
low. The GATE pin will remain low until the voltage on this pin  
rises above the high threshold limit, initiating a new start-up cycle.  
8
VEE  
V
EE – This pin is the negative terminal of the power supply input to  
the circuit.  
VDD This pin is the positive terminal of the power supply input to  
PWRGD Logic  
the circuit.  
Model  
HV302  
Condition  
PWRGD-A/B/C/D  
TD – The resistor connected from this pin to VEE pin sets the time  
INACTIVE (Not Ready)  
ACTIVE (Ready)  
0
1
1
0
VEE  
HI Z  
HI Z  
VEE  
delay from PWRGD-C going active to PWRGD-D going active.  
INACTIVE (Not Ready)  
ACTIVE (Ready)  
TC – The resistor connected from this pin to VEE pin sets the time  
HV312  
delay from PWRGD-B going active to PWRGD-C going active.  
TB – The resistor connected from this pin to VEE pin sets the time  
delay from PWRGD-A going active to PWRGD-B going active.  
RAMP – This pin provides a current output so that a timing ramp  
voltage is generated when a capacitor is connected.  
GATE – This is the Gate Driver Output for the external N-Channel  
MOSFET.  
SENSE – The current sense resistor connected from this pin to VEE  
Pin programs the servo control current limit and the circuit breaker  
trip limit.  
3
Rev. D  
04/17/02  
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 Fax: (408) 222-4895 www.supertex.com  
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