SMH4042A
VCC ≥ 1V
Monitor
VCC
LOW
&
HOST_3V_MON
Input Level
Assert Outputs
LOCAL_PCI_RST &
LOCAL_PCI_RST#
OK
Turn On Signals
DRVREN#,
VGATE3 &
VGATE5
Shut Off Signals
DRVREN#,
HEALTHY#,
SGNL_VLD#,
VGATE3 &
VGATE5
Monitor
CARD_3V_MON &
CARD_3V_MON:
≥ VTRIP?
NO
Monitor
BD_SEL1# &
BD_SEL2#
For Insertion
HIGH
YES
LOW
Turn On
HEALTHY#
Start Timer
tPURST
Monitor
VSEL
LOW
Input Level
HIGH
NO
tPURST
Timeout?
YES
Monitor
HOST_3V_MON
Input Level
LOW
OK
NO
PCI_RST
Released?
YES
Release
Resets
Turn On
SGNL_VLD
2070 Flow01
Flow Chart 1. Sequence Diagram
2070 9.1 5/27/03
SUMMIT MICROELECTRONICS, Inc.
8