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SMH4042ASALN 参数 Datasheet PDF下载

SMH4042ASALN图片预览
型号: SMH4042ASALN
PDF下载: 下载PDF文件 查看货源
内容描述: 分布式电源热插拔控制器的CompactPCI [Distributed Power Hot-Swap Controller for CompactPCI]
分类和应用: 控制器PC
文件页数/大小: 28 页 / 1819 K
品牌: SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
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SMH4042A  
Over-current Circuit Breaker  
RESET CONTROL  
The SMH4042A provides a circuit breaker function to  
protect against short circuit conditions or exceeding the  
supply limits. By placing a series resistor between the  
host supply and the CBI pins, the breakers will trip  
whenever the voltage drop across the series resistor is  
greater than 50mV for more than 16µs.  
While in the power sequencing mode, the reset outputs  
are the last to be released. When they are released all  
conditions of a successful power-up sequence must have  
been met:  
1) VCC and HST_3V_MON are at or above their respec-  
tive VTRIP levels;  
The over-current detection circuit was designed to maxi-  
mize protection while minimizing false alarms. The most  
critical period of time is during the power-on sequence  
when the backend circuits are first being energized. If the  
card has a faulty component or shorted traces, the time  
to shut off should be minimal. However, if the board has  
been operational for a long period of time the likelihood of  
a catastrophic failure occurring is quite low. Therefore,  
theSMH4042Aemploystwodifferentsamplingschemes.  
During power-up the device will sample the current every  
500ns. If eight consecutive over-current conditions are  
detected the VGATE outputs will immediately be shut  
down. This provides an effective response time of 4µs.  
Duringnormaloperation,aftertheFETshavebeenturned  
on, the sampling rate will be adjusted to 2µs, thus  
providing an effective response time of 16µs.  
2) BD_SEL# inputs are low;  
3) CARD_3V_MONandCARD_5V_MONareatorabove  
their respective trip levels;  
4) PWR_EN is high; and  
5) PCI_RST is high.  
The PCI-RST# input must be high for the reset outputs to  
be released. Assuming all of the conditions listed above  
have been met and PCI_RST# is high and tPURST has  
expired, a low input of greater than 40ns duration on the  
PCI_RST# input will initiate a reset cycle. The duration of  
the reset cycle will be determined by the PCI_RST# input.  
If PCI_RST# low is shorter than tPURST, the reset outputs  
will be driven active for tPURST. If PCI_RST# is longer than  
tPURST theresetoutputswillremainactiveuntilPCI_RST#  
is released.  
Also see Figure 3.  
Also see Figure 4.  
PCI_RST#  
t
PRLPR  
t
t
PURST  
PURST  
LOCAL_PCI_RST#  
LOCAL_PCI_RST  
2070 Fig04  
Figure 4. Host-Initiated Reset Timing  
2070 9.1 5/27/03  
SUMMIT MICROELECTRONICS, Inc.  
10  
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