SMH4042A
MEMORY OPERATION
WRITEOPERATIONS
Write Cycle
In Progress
TheSMH4042AallowstwotypesofWriteoperationstoits
a 512 x 8 array: byte Write and page Write. A byte Write
operation writes a single byte during the nonvolatile Write
period (tWR). The page Write operation allows up to 16
Issue Start
bytes in the same page to be written during tWR
.
Issue Stop
Byte Write
Issue Slave
Address and
R/W = 0
After the slave address is sent (to identify the slave
device, and a Read or Write operation), a second byte is
transmitted which contains the 8 bit address of any one
of the 512 words in the array. Upon receipt of the word
address the SMH4042A responds with an Acknowledge.
Afterreceivingthenextbyteofdata,itagainrespondswith
anAcknowledge. Themasterthenterminatesthetransfer
by generating a Stop condition, at which time the
SMH4042A begins the internal write cycle. The
SMH4042A inputs are disabled while the internal write
cycle is in progress, and the device will not respond to any
requests from the Master.
No
ACK
Returned
Yes
Next
Operation
a Write?
No
Yes
Page Write
Issue Stop
TheSMH4042Aiscapableofa16-bytepageWriteopera-
tion. It is initiated in the same manner as the byte-Write
operation, but, instead of terminating the Write cycle after
the first data word, the Master can transmit up to 15 more
bytesofdata. AfterthereceiptofeachbytetheSMH4042A
will respond with an Acknowledge.
Issue
Address
Proceed
With
Write
Await
Next
Command
TheSMH4042Aautomaticallyincrementstheaddressfor
subsequentdatawords. Afterthereceiptofeachwordthe
low order address bits are internally incremented by one.
The high order bits of the address byte remain constant.
Should the Master transmit more than 16 bytes, prior to
generatingtheStopcondition,theaddresscounterwillroll
2070 Flow02
Flow Chart 2. Polling
READOPERATIONS
over and the previously written data will be overwritten. There are two different read options:
As with the byte-Write operation, all inputs are disabled
during the internal write cycle. Refer to Figure 5 for the
1. Current Address Byte Read
address, Acknowledge and data transfer sequence.
2. Random Address Byte Read
Acknowledge Polling
Current Address Read
When the SMH4042A is performing an internal Write The SMH4042A contains an internal address counter
which maintains the address of the last word accessed,
incremented by one. If the last address accessed (either
a Read or Write) was to address location n, the next Read
operationitwillignoreanynewStartconditions. Sincethe
device will only return an acknowledge after it accepts the
Start, the part can be continuously queried until an
acknowledge is issued, indicating that the internal write operation would access data from address location n+1
and increment the current address pointer. When the
SMH4042A receives the Slave address field with the R/W
cycle is complete. See Flow Chart 2 for the proper
sequence of operations for polling.
2070 9.1 5/27/03
SUMMIT MICROELECTRONICS, Inc.
14
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
