SMD1108
Preliminary
REGISTERS
REGISTER READ/WRITE
Even though the ADC cannot be written, performing
commanded conversions (non-auto-monitor mode) re-
quires a dummy Write operation to select the proper
channel and indicate the type of conversion process that
is being requested. The sequence would be: address the
device using 1001 as the DTI followed by the bus address
and a write bit. The next byte contains the conversion
processrequestedandthechannelorchannelgrouptobe
converted.
The registers are read and written using the same 2-wire
bus as the memory. The Configuration Registers and the
GFS Registers are written as shown in Figure 5. Reads
of the registers must be executed like a random Read
operation. That is, a dummy write must be issued in order
to set the address pointer for the following Read.
A
C
A
C
K
A
C
K
Configuration
Register Data
A A A
Register Address
80 thru 9F
1 0 1 1 2 1 0 W K
Single Channel Conversion
S
T
O
P
S
T
A
R
T
The single channel Read allows the host to perform
manual conversions on a single channel. The state of bits
CH2, CH1andCH0selectsone-of-eightchannels. Read-
ing DTI 1001 will return the converted data. If the host
continuesclockingSCLwithoutaninterimStopcommand
the SMD1108 will continue conversions on the selected
channel and output the data as clocked. See the timing
sequence diagrams in Figure 7.
2052 Fig05 1.0
Figure 5. Writing to the Configuration Registers
The Limits Registers for channels 0 through 3 are located
at the top of the ADC address space and utilize the 1001
DTI. Unlike the configuration registers that are limited to
single byte Writes or Reads, the ADC limit registers can
be written in page mode. The example In Figure 6 shows
two byte Writes to configure the CH0 Lower Limit.
Multi-Channel Conversion: 4
Command001willconfigurethechannelconversionsuch
thattheMUXwillswitchchannels0through3sequentially.
Register Address
A
C
A
C
K
A
C
K
F0:
Multi-Channel Conversion: 8
A A A
D D
9 8
1 0 0 1 2 1 0 W K
1 1
0 0 0
1
1
0
x x x x x
x
Command011willconfigurethechannelconversionsuch
thattheMUXwillswitchchannels0through7sequentially.
S
T
O
P
S
T
A
R
T
Differential Conversion
In order to provide a very accurate current sense the
SMD1108 can perform a differential conversion on a
selected CHx/OCx input combination. This is limited to
channels 4 through 7 and their corresponding OC inputs.
The measurement provides the differential voltage be-
tweentheinputchannels(VCC0/CH4toVCC3/CH7)andthe
over-current sense inputs (OC0 to OC3). The result is
that differential noise is rejected and an accurate voltage
drop across the sense resistor is measured.
Register Address
F1:
A
A
A
C
K
A A A
1 0 0 1 2 1 0 W K
C
C D D D D
K
D D D D
7 6 5 4 3 2 1 0
1
1 1
1
0 0 0
1
S
T
O
P
S
T
A
R
T
2052 Fig06 1.0
Figure 6. Writing to the Limits Registers
7
6
5
4
3
2
1
0
Bit
CMD
CH2
CH2
CH1
CH1
x
CH0
Function
0
0
0
1
0
0
1
0
0
1
1
0
CH0
Single channel read mode
Continuous read mode 1
Continuous read mode 2
Differential conversion
x
x
x
1
CH1
CH0
2052 Table03 1.0
Table 3. Command/Address Byte
2052 2.0 10/05/01
SUMMIT MICROELECTRONICS, Inc.
12
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
