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SMD1108 参数 Datasheet PDF下载

SMD1108图片预览
型号: SMD1108
PDF下载: 下载PDF文件 查看货源
内容描述: 8通道的自动监控ADC在系统可编程模拟器件( ISPA )设备 [8-Channel Auto-Monitor ADC In System Programmable Analog (ISPA) Device]
分类和应用: 监控
文件页数/大小: 29 页 / 718 K
品牌: SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
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SMD1108  
Preliminary  
The SMD1108 automatically increments the address for  
subsequentdatawords. Afterthereceiptofeachwordthe  
low order address bits are internally incremented by one.  
The high order bits of the address byte remain constant.  
Should the Master transmit more than 16 bytes, prior to  
generating the Stop condition, the address counter will  
rollover, and the previously written data will be overwrit-  
ten. As with the byte Write operation all inputs are  
disabled during the internal write cycle. Refer to Figure  
2 for the address, Acknowledge, and data transfer se-  
quence.  
Write Cycle  
In Progress  
Issue Start  
Issue Stop  
Issue Slave  
Address and  
R/W = 0  
Acknowledge Polling  
No  
ACK  
When the SMD1108 is performing an internal Write  
operationitwillignoreanynewStartconditions. Sincethe  
device will only return an acknowledge after it accepts the  
Start, the part can be continuously queried until an  
acknowledge is issued, indicating that the internal Write  
cycle is complete. See the flow diagram (Figure 3) for the  
proper sequence of operations for polling.  
Returned  
Yes  
Next  
Operation  
a Write?  
No  
Yes  
READ OPERATIONS  
Issue Stop  
Issue  
Address  
Read operations are initiated with the R/W bit of the  
identification field set to 1. There are two different Read  
options: (1) Current Address Byte Read; or (2) Random  
Address Byte Read  
Proceed  
With  
Write  
Await  
Next  
Command  
Current Address Read  
TheSMD1108containsaninternaladdresscounterwhich  
maintains the address of the last word accessed, incre-  
2052 Fig03  
Figure 3. Polling Sequence  
S
T
A
R
T
S
T
O
P
Typical Write Operation  
Master  
SDA  
R
/
W
A A A  
2 1  
A A A A A A A A  
7 6  
D D D D D D D D  
D D  
D D  
1 0  
0
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
A
C
K
A
C
K
A
C
K
A
C
K
Slave  
S
T
A
R
T
Typical Read Operation  
S
T
O
P
N
A
C
K
A
C
K
A
C
K
Master  
SDA  
R
/
W
A A A  
2 1  
D D D D D D D D  
D D D D D D D D  
D D  
D D  
1 0  
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
A
C
K
Slave  
2052 Fig02 2.0  
Figure 2. Address, Acknowledge and Data Transfer Sequence  
2052 2.0 10/05/01  
SUMMIT MICROELECTRONICS, Inc.  
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