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S93462SA 参数 Datasheet PDF下载

S93462SA图片预览
型号: S93462SA
PDF下载: 下载PDF文件 查看货源
内容描述: 精密电源电压监控和复位控制器 [Precision Supply-Voltage Monitor and Reset Controller]
分类和应用: 监控控制器
文件页数/大小: 14 页 / 150 K
品牌: SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
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S93462/S93463  
The format for all instructions is: one start bit; two op  
code bits and either six (x16) or seven (x8) address or  
instruction bits.  
Write  
After receiving a WRITE command, address and the  
data, the CS (Chip Select) pin must be deselected for a  
minimum of 250ns (tCSMIN). The falling edge of CS will  
start automatic erase and write cycle to the memory  
location specified in the instruction. The ready/busy  
status of the S93462/463 can be determined by select-  
ing the device and polling the DO pin.  
Read  
Upon receiving a READ command and an address  
(clocked into the DI pin), the DO pin of the S93462/463  
will come out of the high impedance state and, will first  
output an initial dummy zero bit, then begin shifting out  
the data addressed (MSB first). The output data bits  
will toggle on the rising edge of the SK clock and  
are stable after the specified time delay  
(tPD0 or tPD1).  
Erase  
Upon receiving an ERASE command and address, the  
CS (Chip Select) pin must be deselected for a minimum  
of 250ns (tCSMIN). The falling edge of CS will start the  
auto erase cycle of the selected memory location. The  
ready/busy status of the S93462/463 can be deter-  
mined by selecting the device and polling the DO pin.  
Once cleared, the content of a cleared location returns  
to a logical 1state.  
t
t
t
SKLOW  
CSH  
SKHI  
SK  
t
t
DIH  
DIS  
VALID  
VALID  
DI  
t
CSS  
CS  
t
t
t
t
DIS  
CSMIN  
PD0, PD1  
DO  
DATAVALID  
2021 ILL 3 1.0  
Figure 1. Sychronous Data Timing  
SK  
t
CS  
CS  
DI  
STANDBY  
A
N
A
N1  
A
0
1
1
0
t
HZ  
t
HIGH-Z  
HIGH-Z  
PD0  
DO  
0
D
N
D
N1  
D
1
D
0
2021 ILL4 1.0  
Figure 2. Read Instruction Timing  
3
Summit Microelectronics, Inc.  
2021 4.2 1/23/01