S93462/S93463
PIN CONFIGURATION
During power-up, the reset outputs remain active until
VCC reaches the VTRIP threshold. The outputs will con-
tinue to be driven for approximately 150ms after reach-
ing VTRIP. The reset outputs will be valid so long as VCC
is ≥ 1.0V. During power-down, the reset outputs will
8-Pin SOIC
begin driving active when VCC falls below VTRIP
.
1
2
3
4
8
7
6
5
V
CC
CS
SK
DI
The reset pins are I/Os; therefore, the S93462/463 can
RESET
RESET#
GND
act as a signal conditioning circuit for an externally
applied reset. The inputs are edge triggered; that is, the
RESET input will initiate a reset time-out after detecting
a low to high transition and the RESET# input will initiate
a reset time-out after detecting a high to low transition.
DO
2021 T PCon 2.0
Refer to the applications Information section for more
details on device operation as a debounce/reset ex-
tender circuit.
It should be noted the reset outputs are open drain.
When used as outputs driving a circuit they need to be
either tied high (RESET#) or tied to ground (RESET)
through the use of pull-up or pull-down resistors. Refer
to the applications aid section for help in determining the
value of resistor to be used. Internally these pins are
weakly pulled up (RESET#) and pulled down (RESET):
PIN FUNCTIONS
Pin Name
Function
therefore, if the signals are not being used the pins may
be left unconnected.
CS
Chip Select
SK
Clock Input
GENERAL OPERATION
The S93462/463 is a 1024-bit nonvolatile memory
intended for use with industry standard microproces-
sors. The S93463 is organized as X16, seven 9-bit
instructions control the reading, writing and erase
operations of the device. The S93462 is organized as
X8, seven 10-bit instructions control the reading, writing
anderaseoperationsofthedevice. Thedeviceoperates
onasingle3Vor5Vsupplyandwillgenerateonchip, the
high voltage required during any write operation.
DI
Serial Data Input
Serial Data Output
+2.7 to 6.0V Power Supply
Ground
DO
VCC
GND
RESET/RESET#
RESET I/O
DEVICE OPERATION
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
APPLICATIONS
The S93462/463 is ideal for applications requiring low
voltage and low power consumption. This device pro-
vides microcontroller RESET control and can be manu-
ally resettable.
The ready/busy status can be determined after the start
ofawriteoperationbyselectingthedevice(CShigh)and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. See the
Applications Aid section for detailed use of the ready
busy status.
RESET CONTROLLER DESCRIPTION
The S93462/463 provides a precision reset controller
that ensures correct system operation during brownout
andpower-up/-downconditions. Itisconfiguredwithtwo
open drain reset outputs; pin 7 is an active high output
and pin 6 is an active low output.
2
2021 4.2 1/23/01
Summit Microelectronics, Inc.
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
