S39421
SK
t
CS
CS
DI
STANDBY
A
N
A
N–1
A
0
1
1
0
t
HZ
t
HIGH-Z
HIGH-Z
PD0
DO
0
D
N
D
N–1
D
1
D
0
2024 ILL20.0
FIGURE 6. READ INSTRUCTION TIMING
SK
t
CS
STANDBY
CS
DI
STATUS
VERIFY
A
N
A
N-1
A
0
D
N
D
0
1
0
1
t
t
SV
HZ
BUSY
HIGH-Z
DO
READY
HIGH-Z
t
EW
2024 ILL21.0
FIGURE 7. WRITE INSTRUCTION TIMING
Write All
Erase/Write Enable and Disable
The memory powers up in the write disable state. Any UponreceivingaWRALcommandanddata,theCS(Chip
writing after power-up or after an EWDS (write disable) Select) pin must be deselected for a minimum of 250ns
instruction must first be preceded by the EWEN (write (tCSMIN). The falling edge of CS will start the self clocking
enable) instruction. Once the write instruction is enabled, data write to all memory locations in the device. The
itwillremainenableduntilpowertothedeviceisremoved, clockingoftheSKpinisnotnecessaryafterthedevicehas
or the EWDS instruction is sent. The EWDS instruction entered the self clocking mode. The ready/busy status of
can be used to disable all S39421 write and clear instruc- the S39421 can be determined by selecting the device
tions, and will prevent any accidental writing or clearing of and polling the DO pin. It is not necessary for all memory
the device. Data can be read normally from the device locations to be cleared before the WRAL command is
regardless of the write enable/disable status.
executed.
2024 9.0 8/8/00
11
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
