S39421
MEMORY OPERATION
incrementing the address and outputting data so long as
CS stays high. If the highest address is reached, the
address counter will roll over to address 0000. CS going
low will reset the instruction register and any subsequent
read must be initiated in the normal manner of issuing the
command and address.
The S39421 has a 1024-bit nonvolatile memory
intended for use with industry standard microprocessors.
The memory is organized as X16, seven 9-bit instructions
control the reading, writing and erase operations of the
device. The device operates on a single 3V or 5V supply
andwillgenerateonchip, thehighvoltagerequiredduring
any write operation.
Write
AfterreceivingaWRITEcommand,addressandthedata,
the CS (Chip Select) pin must be deselected for a mini-
mum of 250ns (tCSMIN). The falling edge of CS will start
automatic write cycle to the memory location specified in
the instruction. The ready/busy status can be determined
by selecting the device and polling the DO pin.
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO pin
is normally in a high impedance state except when read-
ingdatafromthedevice,orwhencheckingtheready/busy
status after a write operation.
Theready/busystatuscanbedeterminedafterthestartof
a write operation by selecting the memory and polling the
DO pin; DO low indicates that the write operation is not
completed, while DO high indicates that the device is
ready for the next instruction.
Page Write
AssumeWENhasbeenissued.ThehostwillthentakeCS
high, and begin clocking in the start bit, write command
and 6-bit address immediately followed by the first 16-bit
word of data to be written. The host can then continue
clocking in 16-bit words of data with each word to be
written to the next higher address. Internally the address
pointer is incremented after receiving each group of
sixteen clocks; however, once the address counter
reaches xxx x111 it will roll over to xx x000 with the next
clock. After the last bit is clocked in no internal write
operation will occur until CS is brought low.
The format for all instructions is: one start bit; two op code
bits and either six address or instruction bits.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin will come out of the
highimpedancestateand,willfirstoutputaninitialdummy
zero bit, then begin shifting out the data addressed (MSB
first). The output data bits will toggle on the rising edge of
the SK clock and are stable after the specified time delay
(tPD0 or tPD1).
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deselected for a minimum
of250ns(tCSMIN). ThefallingedgeofCSwillstartthe auto
erase cycle of the selected memory location. The ready/
busy status can be determined by selecting the device
and polling the DO pin. Once cleared, the content of a
cleared location returns to a logical “1” state.
Continuous Read
This begins just like a standard read with the host issuing
a read instruction and clocking out the data byte [word]. If
the host then keeps CS high and continues generating
clocks on SK, the S39421 will output data from the next
higher address location. The S39421 will continue
t
t
t
SKLOW
CSH
SKHI
SK
t
t
DIH
DIS
VALID
VALID
DI
t
CSS
CS
t
t
t
t
DIS
CSMIN
PD0, PD1
DO
DATAVALID
2024 ILL19.0
FIGURE 5. SYCHRONOUS DATA TIMING
2024 9.0 8/8/00
10
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
