TS5070 - TS5071
DEFINITIONS AND TIMING CONVENTIONS
DEFINITIONS
VIH
VIH is the D.C. input level above which an input level is guaranteed to appear as a logical one.
This parameter is to be measured by performing a functional test at reduced clock speeds and
nominal timing (i.e. not minimum setup and hold times or output strobes), with the high level of
all driving signals set to VIH and maximum supply voltages applied to the device.
VIL
VIL is the D.C. input level below which an input level is guaranteed to appear as a logical zero
the device. This parameter is measured in the same manner as V but with all driving signal
IH
low levels set to VIL and minimum supply voltage applied to the device.
VOH
VOL
VOH is the minimmum D.C. output level to which an output placed in a logical one state will
converge when loaded at the maximum specified load current.
VOL is the maximum D.C. output level to which an output placed in a logical zero state will
converge when loaded at the maximum specified load current.
Threshold Region
Valid Signal
The threshold region is the range of input voltages between VIL and VIH.
A signal is Valid if it is in one of the valid logic states. (i.e. above VIH or below VIL). In timing
specifications, a signal is deemed valid at the instant it enters a valid state.
Invalid signal
A signal is invalid if it is not in a valid logic state, i.e., when it is in the threshold region between
VIL and VIH. In timing specifications, a signal is deemed Invalid at the instant it enters the
threshold region.
TIMING CONVENTIONS
For the purpose of this timing specifications the following conventions apply :
Input Signals
Period
All input signals may be characterized as : VL = 0.4 V, VH = 2.4 V, tR < 10 ns, tF < 10 ns.
The period of the clock signal is designated as tPxx where xx represents the mnemonic of the
clock signal being specified.
Rise Time
Rise times are designated as tRyy, where yy represents a mnemonic of the signal whose rise
time is being specified, tRyy is measured from VIL to VIH.
Fall Time
Fall times are designated as tFyy, where yy represents a mnemonic of the signal whose fall
time is being specified, tFyy is measured from VIH to VIL.
Pulse Width High
The high pulse width is designated as tWzzH, where zz represents the mnemonic of the input
or output signal whose pulse width is being specified. High pulse width are measured from VIH
to VIH.
Pulse Width Low
Setup Time
The low pulse is designated as tWzzL’ where zz represents the mnemonic of the input or output
signal whose pulse width is being specified. Low pulse width are measured from V to VIL.
IL
Setup times are designated as tSwwxx where ww represents the mnemonic of the input signal
whose setup time is being specified relative to a clock or strobe input represented by mnemonic
xx. Setup times are measured from the ww Valid to xx Invalid.
Hold Time
Hold times are designated as THwwxx where ww represents the mnemonic of the input signal
whose hold time is being specified relative to a clock or strobe input represented by the
mnemonic xx. Hold times are measured from xx Valid to ww Invalid
Delay Time
Delay times are designated as TDxxyy [H/L], where xx represents the mnemonic of the input
reference signal and yy represents the mnemonic of the output signal whose timing is being
specified relative to xx. The mnemonic may optionally be terminated by an H or L to specify the
high going or low going transition of the output signal. Maximum delay times are measured from
xx Valid to yy Valid. Minimum delay times are measured from xx Valid to yy Invalid. This
parameter is tested under the load conditions specified in the Conditions column of the Timing
Specifications section of this datasheet.
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STMICROELECTRONICS [ ST ]
