I2C Bus specification
TDA7719
2
5
I C Bus specification
5.1
Interface protocol
The interface protocol comprises:
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a start condition (S)
a chip address byte (the LSB determines read/write transmission)
a subaddress byte
a sequence of data (N-bytes + acknowledge)
a stop condition (P)
the max. clock speed is 500kbits/s
3.3V logic compatible
5.1.1
Receive mode
S
1 0 0 0 1 0
0
R/W ACK TS
X
AI A4 A3 A2 A1 A0 ACK DATA ACK
P
S = Start
R/W =
"0" -> Receive Mode (Chip can be programmed by µP)
"1" -> Transmission Mode (Data could be received by µP)
ACK = Acknowledge
P = Stop
TS = Testing mode
AI = Auto increment
5.1.2
Transmission mode
S
1
0
0
0
1
0
0
R/W
ACK
X
X
X
X
X
X
BZ SM
ACK
P
SM = Soft mute activated for main channel
BZ = Softstep Busy (‘0’ = Busy)
X = Not Used
The transmitted data is automatic updated after each ACK. Transmission can be repeated
without new chip address.
5.1.3
Reset condition
A Power-On-Reset is invoked if the supply voltage is below than 3.5V. After that the registers
are initialized to the default data written in following tables.
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STMICROELECTRONICS [ ST ]
