STM8S903K3 STM8S903F3
Interrupt vector mapping
7
Interrupt vector mapping
Table 10: Interrupt mapping
IRQ Source
no. block
Description
Wakeup from Wakeup from
Vector address
halt mode
active-halt
mode
RESET
TRAP
Reset
Yes
-
Yes
-
0x00 8000
0x00 8004
0x00 8008
0x00 800C
0x00 8010
0x00 8014
0x00 8018
0x00 801C
0x00 8020
0x00 8024
0x00 8028
0x00 802C
0x00 8030
0x00 8034
Software interrupt
0
1
2
3
4
5
6
7
8
9
TLI
External top level interrupt
Auto wake up from halt
Clock controller
-
-
AWU
CLK
-
Yes
-
-
EXTI0
EXTI1
EXTI2
EXTI3
EXTI4
EXTI5
Port A external interrupts
Port B external interrupts
Port C external interrupts
Port D external interrupts
Port E external interrupts
Port F
Yes(1)
Yes
Yes
Yes
Yes
Yes(1)
Yes
Yes
Yes
Yes
Reserved
-
-
10 SPI
End of transfer
Yes
Yes
-
11 TIM1
TIM1 update/ overflow/ underflow/ -
trigger/ break
12 TIM1
13 TIM5
14 TIM5
15
TIM1 capture/ compare
TIM5 update/ overflow/ trigger
TIM5 capture/ compare
Reserved
-
-
0x00 8038
0x00 803C
0x00 8040
0x00 8044
0x00 8048
0x00 804C
0x00 8050
0x00 8054
0x00 8058
0x00 805C
-
-
-
-
-
-
16
Reserved
-
-
17 UART1
18 UART1
19 I2C
20
Tx complete
-
-
Receive register DATA FULL
I2C interrupt
-
-
Yes
Yes
Reserved
-
-
-
-
21
Reserved
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