Pinouts and pin descriptions
STM8S003F3 STM8S003K3
Table 6. STM8S003F3 pin description (continued)
Pin
no.
Input
Output
Main
function
(after
Alternate
function
after remap
[option bit]
Default
alternate
function
Pin name
Type
High
OD PP
reset)
sink(1)
Configurable
clock
output/Timer inverted
1 - channel
4/Analog
input 2
PC4/CLK_CCO/
TIM1_
CH4/AIN2/
Timer 1 -
11
I/O
X
X
X
HS
O3
X
X
Port C4
14
channel 2
[AFR7]
[TIM1_ CH2N]
Timer 2 -
channel 1
[AFR0]
PC5/ SPI_SCK
[TIM2_ CH1]
12
13
14
I/O
I/O
X
X
X
X
X
X
HS
HS
O3
O3
X
X
X
X
Port C5 SPI clock
15
16
Timer 1 -
channel 1
[AFR0]
PC6/ SPI_MOSI
[TIM1_ CH1]
SPI master
Port C6
out/slave in
Timer 1 -
channel 2
[AFR0]
PC7/ SPI_MISO
[TIM1_ CH2]
SPI master
Port C7
I/O
I/O
X
X
X
X
X
X
X
X
X
HS
HS
HS
O3
O4
O3
X
X
X
X
X
X
17
18
19
in/ slave out
SWIM data
Port D1
15 PD1/ SWIM(4)
-
interface
Timer 2 -
channel 3
[AFR1]
PD2/AIN3/
16
Analog input
I/O
Port D2
3
[TIM2_ CH3]
Analog input
4/ Timer 2 -
channel
2/ADC
external
trigger
PD3/ AIN4/
17 TIM2_ CH2/
ADC_ ETR
I/O
X
X
X
HS
O3
X
X
Port D3
-
20
1. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the
total driven current must respect the absolute maximum ratings.
2. When the MCU is in halt/active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for
waking up the device. In this mode, the output state of PA1 is not driven. It is recommended d to use PA1 only in input mode
if halt/active-halt is used in the application.
3. In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are
not implemented).
4. The PD1 pin is in input pull-up during the reset phase and after internal reset release.
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DocID018576 Rev 5
STMICROELECTRONICS [ ST ]
