STM8S003K3 STM8S003F3
Symbol Parameter
Electrical characteristics
Unit
Standard mode I2C
Fast mode I2C(1)
Min(2)
Max(2) Min(2)
Max(2)
tsu(STO) STOP condition setup time
4.0
0.6
1.3
tw(STO:STA) STOP to START condition time
(bus free)
4.7
μs
pF
Cb
Capacitive load for each bus line
400
400
(1)
f
, must be at least 8 MHz to achieve max fast I2C speed (400kHz)
MASTER
(2) Data based on standard I2C protocol requirement, not tested in production
(3) The maximum hold time of the start condition has only to be met if the interface does not stretch the
low time
(4) The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
the undefined region of the falling edge of SCL
Figure 41: Typical application with I2C bus and timing diagram
V
V
DD
DD
STM8S
4.7kΩ
4.7kΩ
100Ω
100Ω
SDA
SCL
2
I
C bus
REPEATED
START
START
t
t
w(STO:STA)
su(STA)
START
SDA
t
t
r(SDA)
f(SDA)
t
t
h(SDA)
su(SDA)
STOP
SCL
t
t
t
t
t
su(STO)
t
h(STA)
w(SCLH)
w(SCLL)
r(SCL)
f(SCL)
ai17490
1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD.
9.3.10
10-bit ADC characteristics
Subject to general operating conditions for VDD, fMASTER, and TA unless otherwise specified.
DocID018576 Rev 2
81/99
STMICROELECTRONICS [ ST ]
