STM8S003K3 STM8S003F3
Interrupt vector mapping
7
Interrupt vector mapping
Table 10: Interrupt mapping
IRQ Source
no. block
Description
Wakeup from Wakeup from
Vector address
halt mode
active-halt mode
RESET Reset
Yes
Yes
0x00 8000
0x00 8004
0x00 8008
0x00 800C
0x00 8010
0x00 8014
0x00 8018
0x00 801C
0x00 8020
0x00 8024
0x00 8028
0x00 802C
0x00 8030
0x00 8034
TRAP
TLI
Software interrupt
-
-
0
External top level interrupt
Auto wake up from halt
Clock controller
-
-
1
AWU
CLK
-
Yes
2
-
-
3
EXTI0
EXTI1
EXTI2
EXTI3
EXTI4
Port A external interrupts
Port B external interrupts
Port C external interrupts
Port D external interrupts
Port E external interrupts
Reserved
Yes(1)
Yes
Yes
Yes
Yes
-
Yes(1)
Yes
Yes
Yes
Yes
-
4
5
6
7
8
9
Reserved
-
-
10
11
SPI
End of transfer
Yes
-
Yes
-
TIM1 update/ overflow/ underflow/
trigger/ break
TIM1
12
13
14
15
16
17
18
19
20
21
22
TIM1
TIM2
TIM2
TIM1 capture/ compare
TIM2 update/ overflow
TIM2 capture/ compare
Reserved
-
-
0x00 8038
0x00 803C
0x00 8040
0x00 8044
0x00 8048
0x00 804C
0x00 8050
0x00 8054
0x00 8058
0x00 805C
0x00 8060
-
-
-
-
-
-
Reserved
-
-
UART1 Tx complete
-
-
UART1 Receive register DATA FULL
-
-
I2C
I2C interrupt
Reserved
Reserved
Yes
Yes
-
-
-
-
-
-
ADC1 end of conversion/ analog
watchdog interrupt
ADC1
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