STM8S003K3 STM8S003F3
Option bytes
8
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in the table below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP
option that can only be modified in ICP mode (via SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication
protocol and debug module user manual (UM0470) for information on SWIM programming
procedures.
Table 11: Option bytes
Addr.
Option
name
Option Option bits
byte no.
Factory
default
setting
7
6
5
4
3
2
1
0
0x4800 Read-out
protection
OPT0
ROP [7:0]
0x00
(ROP)
0x4801 User boot
code(UBC)
0x4802
OPT1
UBC [7:0]
0x00
0xFF
0x00
NOPT1 NUBC [7:0]
OPT2 AFR7 AFR6
NOPT2 NAFR7
AFR5
AFR4
AFR3
AFR2
AFR1
AFR0
NAFR0
0x4803 Alternate
function
0x4804
NAFR6 NAFR5 NAFR4
NAFR3
NAFR2 NAFR1
0xFF
remapping
(AFR)
0x4805h Miscell.
option
OPT3
Reserved
HSI
TRIM
LSI_ EN
IWDG
_HW
WWDG WWDG
_HW _HALT
0x00
0xFF
0x00
0xFF
0x4806
NOPT3 Reserved
NHSI
TRIM
NLSI_
EN
NIWDG NWWDG NWW
_HW _HW G_HALT
0x4807 Clock
option
OPT4
Reserved
EXT CLK CKAWU PRS C1 PRS C0
SEL
0x4808
NOPT4 Reserved
NEXT
CLK
NCKA
WUSEL
NPRSC1 NPR
SC0
0x4809 HSE clock OPT5
startup
HSECNT [7:0]
0x00
0xFF
0x480A
NOPT5 NHSECNT [7:0]
Table 12: Option byte description
Description
Option byte no.
OPT0
ROP[7:0] Memory readout protection (ROP)
0xAA: Enable readout protection (write access via SWIM protocol)
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