STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
5.3.2
Operating conditions at power-up / power-down
The parameters given in
are derived from tests performed under the ambient
temperature condition summarized in
Table 11.
Symbol
t
VDD
Operating conditions at power-up / power-down
Parameter
V
DD
rise time rate
V
DD
fall time rate
Conditions
Min
0
20
Max
Unit
µs/V
5.3.3
Embedded reset and power control block characteristics
The parameters given in
are derived from tests performed under ambient
temperature and V
DD
supply voltage conditions summarized in
Table 12.
Symbol
Embedded reset and power control block characteristics
Parameter
Conditions
PLS[2:0]=000 (rising edge)
PLS[2:0]=000 (falling edge)
PLS[2:0]=001 (rising edge)
PLS[2:0]=001 (falling edge)
PLS[2:0]=010 (rising edge)
PLS[2:0]=010 (falling edge)
PLS[2:0]=011 (rising edge)
Min
2.1
2
2.19
2.09
2.28
2.18
2.38
2.28
2.47
2.37
2.57
2.47
2.66
2.56
2.76
2.66
Typ
2.18
2.08
2.28
2.18
2.38
2.28
2.48
2.38
2.58
2.48
2.68
2.58
2.78
2.68
2.88
2.78
100
Falling edge
Rising edge
1.8
(1)
1.88
1.84
1.92
40
1
2.5
4.5
1.96
2.0
Max
2.26
2.16
2.37
2.27
2.48
2.38
2.58
2.48
2.69
2.59
2.79
2.69
2.9
2.8
3
2.9
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mV
V
V
mV
mS
V
PVD
Programmable voltage
detector level selection
PLS[2:0]=011 (falling edge)
PLS[2:0]=100 (rising edge)
PLS[2:0]=100 (falling edge)
PLS[2:0]=101 (rising edge)
PLS[2:0]=101 (falling edge)
PLS[2:0]=110 (rising edge)
PLS[2:0]=110 (falling edge)
PLS[2:0]=111 (rising edge)
PLS[2:0]=111 (falling edge)
V
PVDhyst(2)
V
POR/PDR
V
PDRhyst(2)
PVD hysteresis
Power on/power down
reset threshold
PDR hysteresis
T
RSTTEMPO(2)
Reset temporization
2. Guaranteed by design, not tested in production.
1. The product behavior is guaranteed by design down to the minimum V
POR/PDR
value.
Doc ID 14611 Rev 7
43/123
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