Electrical characteristics
Figure 30. Typical connection diagram using the ADC
VDD
VT
0.6 V
AINx
Cparasitic
VT
0.6 V
IL±1 µA
STM32F103x4, STM32F103x6
RAIN(1)
STM32F103xx
Sample and hold ADC
converter
RADC(1)
12-bit
converter
CADC(1)
VAIN
ai14150c
1. Refer to
Table 45
AIN
, R
ADC
and C
ADC
.
2. C
parasitic
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high C
parasitic
value will downgrade conversion accuracy. To remedy
this, f
ADC
should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown inFigure
or
Figure 32,
depending on whether V
REF+
is connected to V
DDA
or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 31. Power supply and reference decoupling (V
REF+
not connected to
V
DDA
)
1. The V
REF+
input is available only on the TFBGA64 package.
66/80
Doc ID 15060 Rev 3
STMICROELECTRONICS [ STMICROELECTRONICS ]
