STM32F103x4, STM32F103x6
Electrical characteristics
5.3.17
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 45 are derived from tests
performed under the ambient temperature, f
frequency and V
supply voltage
PCLK2
DDA
conditions summarized in Table 9.
Note:
It is recommended to perform a calibration after each power-up.
Table 45. ADC characteristics
Symbol
Parameter
Power supply
Conditions
Min
Typ
Max
Unit
VDDA
2.4
2.4
3.6
VDDA
220(1)
14
V
V
(3)
VREF+
Positive reference voltage
Current on the VREF input pin
ADC clock frequency
IVREF
160(1)
µA
MHz
(3)
fADC
0.6
(2)
Sampling rate
0.05
1
MHz
fS
f
ADC = 14 MHz
823
17
kHz
(2)
External trigger frequency
fTRIG
1/fADC
0 (VSSA tied to
ground)
(3)
Conversion voltage range
VREF+
V
VAIN
See Equation 1 and
Table 46 for details
(2)
RAIN
External input impedance
Sampling switch resistance
50
1
k
k
pF
(2)
RADC
Internal sample and hold
capacitor
(2)
8
CADC
fADC = 14 MHz
fADC = 14 MHz
fADC = 14 MHz
5.9
83
µs
1/fADC
µs
(2)
Calibration time
tCAL
0.214
3(4)
Injection trigger conversion
latency
(2)
tlat
1/fADC
µs
0.143
2(4)
Regular trigger conversion
latency
(2)
tlatr
1/fADC
µs
f
f
ADC = 14 MHz
ADC = 14 MHz
0.107
1.5
0
17.1
239.5
1
(2)
Sampling time
Power-up time
tS
1/fADC
µs
(2)
tSTAB
0
1
18
µs
Total conversion time
(including sampling time)
(2)
tCONV
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1. Based on characterization, not tested in production.
2. Guaranteed by design, not tested in production.
3. In devices delivered in VFQFPN and LQFP packages, VREF+ is internally connected to VDDA and VREF- is internally
connected to VSSA. Devices that come in the TFBGA64 package have a VREF+ pin but no VREF- pin (VREF- is internally
connected to VSSA), see Table 5 and Figure 4.
4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 45.
Doc ID 15060 Rev 3
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