STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
(1)(2)
Table 36. Synchronous multiplexed PSRAM write timings
Symbol Parameter
tw(CLK)
Min
27.7
Max
Unit
FSMC_CLK period
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(CLKL-NExL)
td(CLKH-NExH)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FSMC_CLK low to FSMC_Nex low (x = 0...2)
FSMC_CLK high to FSMC_NEx high (x = 0...2)
FSMC_CLK low to FSMC_NADV low
2
THCLK + 2
4
FSMC_CLK low to FSMC_NADV high
5
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
FSMC_CLK high to FSMC_Ax invalid (x = 16...25)
FSMC_CLK low to FSMC_NWE low
0
td(CLKH-AIV)
TCK + 2
THCLK +1
3
td(CLKL-NWEL)
td(CLKH-NWEH)
td(CLKL-ADV)
td(CLKL-ADIV)
td(CLKL-Data)
1
FSMC_CLK high to FSMC_NWE high
FSMC_CLK low to FSMC_AD[15:0] valid
FSMC_CLK low to FSMC_AD[15:0] invalid
FSMC_A/D[15:0] valid after FSMC_CLK low
12
6
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high
7
2
1
th(CLKH-NWAITV)
td(CLKL-NBLH)
FSMC_NWAIT valid after FSMC_CLK high
FSMC_CLK low to FSMC_NBL high
1. CL = 15 pF.
2. Based on characterization, not tested in production.
Doc ID 14611 Rev 7
69/123
STMICROELECTRONICS [ ST ]
