Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FSMC_CLK
t
t
d(CLKL-NExL)
d(CLKH-NExH)
Data latency = 1
d(CLKL-NADVH)
FSMC_NEx
t
t
d(CLKL-NADVL)
FSMC_NADV
t
t
d(CLKH-AIV)
d(CLKL-AV)
FSMC_A[25:0]
FSMC_NOE
t
t
d(CLKL-NOEL)
d(CLKH-NOEH)
t
t
su(DV-CLKH)
h(CLKH-DV)
t
t
h(CLKH-DV)
su(DV-CLKH)
FSMC_D[15:0]
FSMC_NWAIT
D1
D2
t
t
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
(WAITCFG = 1b, WAITPOL + 0b)
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
ai14894d
(1)(2)
Table 37. Synchronous non-multiplexed NOR/PSRAM read timings
Symbol Parameter Min
tw(CLK) 27.7
Max
Unit
FSMC_CLK period
ns
ns
ns
ns
ns
ns
ns
td(CLKL-NExL)
td(CLKH-NExH)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
FSMC_CLK high to FSMC_NEx high (x = 0...2)
FSMC_CLK low to FSMC_NADV low
1.5
4
THCLK + 2
FSMC_CLK low to FSMC_NADV high
5
FSMC_CLK low to FSMC_Ax valid (x = 0...25)
0
td(CLKH-AIV)
FSMC_CLK high to FSMC_Ax invalid (x = 0...25) THCLK + 4
FSMC_CLK low to FSMC_NOE low
td(CLKL-NOEL)
td(CLKH-NOEH)
tsu(DV-CLKH)
th(CLKH-DV)
THCLK + 1.5 ns
FSMC_CLK high to FSMC_NOE high
THCLK + 1.5
ns
ns
ns
ns
ns
FSMC_D[15:0] valid data before FSMC_CLK high 6.5
FSMC_D[15:0] valid data after FSMC_CLK high
7
7
2
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_SMCLK high
th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high
1. CL = 15 pF.
2. Based on characterization, not tested in production.
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Doc ID 14611 Rev 7
STMICROELECTRONICS [ ST ]
