STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms
t
w(NE)
FSMC_NEx
FSMC_NOE
t
t
t
h(NE_NWE)
v(NWE_NE)
w(NWE)
FSMC_NWE
t
tv(A_NE)
h(A_NWE)
FSMC_A[25:16]
Address
tv(BL_NE)
t
h(BL_NWE)
FSMC_NBL[1:0]
FSMC_AD[15:0]
NBL
t
t
h(Data_NWE)
t
v(A_NE)
v(Data_NADV)
Address
Data
t
th(AD_NADV)
v(NADV_NE)
t
w(NADV)
FSMC_NADV
ai14891B
(1)(2)
Table 34. Asynchronous multiplexed PSRAM/NOR write timings
Symbol
tw(NE)
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
Parameter
FSMC_NE low time
Min
Max
Unit
5THCLK – 1
2THCLK
5THCLK + 2
2THCLK + 1
2THCLK + 2
ns
ns
ns
ns
ns
ns
ns
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low time
2THCLK – 1
THCLK – 1
FSMC_NWE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
7
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low
3
5
tw(NADV)
FSMC_NADV low time
THCLK – 1
THCLK + 1
FSMC_AD (address) valid hold time after
FSMC_NADV high
th(AD_NADV)
T
HCLK – 3
ns
th(A_NWE)
tv(BL_NE)
Address hold time after FSMC_NWE high
FSMC_NEx low to FSMC_BL valid
4THCLK
ns
ns
ns
1.6
th(BL_NWE)
FSMC_BL hold time after FSMC_NWE high
THCLK – 1.5
tv(Data_NADV) FSMC_NADV high to Data valid
THCLK + 1.5 ns
ns
th(Data_NWE) Data hold time after FSMC_NWE high
THCLK – 5
1. CL = 15 pF.
2. Based on characterization, not tested in production.
Doc ID 14611 Rev 7
65/123
STMICROELECTRONICS [ ST ]
