STM32F105xx, STM32F107xx
Electrical characteristics
Figure 20. SPI timing diagram - slave mode and CPHA = 0
NSS input
t
c(SCK)
t
t
h(NSS)
SU(NSS)
CPHA=0
CPOL=0
t
w(SCKH)
w(SCKL)
CPHA=0
CPOL=1
t
t
t
t
t
t
t
dis(SO)
r(SCK)
f(SCK)
v(SO)
a(SO)
h(SO)
MISO
MSB O UT
BI T6 OUT
BIT1 IN
LSB OUT
OUT PUT
t
su(SI)
MOSI
M SB IN
LSB IN
INPUT
t
h(SI)
ai14134c
(1)
Figure 21. SPI timing diagram - slave mode and CPHA = 1
NSS input
t
t
t
SU(NSS)
c(SCK)
h(NSS)
CPHA=1
CPOL=0
t
w(SCKH)
w(SCKL)
CPHA=1
CPOL=1
t
t
t
r(SCK)
f(SCK)
t
t
t
v(SO)
h(SO)
dis(SO)
t
a(SO)
MISO
MSB O UT
BI T6 OUT
LSB OUT
OUT PUT
t
t
su(SI)
h(SI)
MOSI
M SB IN
BIT1 IN
LSB IN
INPUT
ai14135
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
Doc ID 15274 Rev 4
61/95
STMICROELECTRONICS [ ST ]
