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STM32F105RBT6 参数 Datasheet PDF下载

STM32F105RBT6图片预览
型号: STM32F105RBT6
PDF下载: 下载PDF文件 查看货源
内容描述: [Mainstream Connectivity line, ARM Cortex-M3 MCU with 128 Kbytes Flash, 72 MHz CPU, CAN, USB 2.0 OTG]
分类和应用: 以太网通信
文件页数/大小: 95 页 / 1009 K
品牌: STMICROELECTRONICS [ ST ]
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Electrical characteristics  
STM32F105xx, STM32F107xx  
5.3.4  
Embedded reference voltage  
The parameters given in Table 12 are derived from tests performed under ambient  
temperature and V supply voltage conditions summarized in Table 9.  
DD  
Table 12. Embedded internal reference voltage  
Symbol  
Parameter  
Conditions  
Min  
Max  
Unit  
Typ  
–40 °C < TA < +105 °C 1.16 1.20  
–40 °C < TA < +85 °C 1.16 1.20  
1.26  
1.24  
V
V
VREFINT Internal reference voltage  
ADC sampling time when  
reading the internal reference  
voltage  
(1)  
17.1(2)  
TS_vrefint  
5.1  
µs  
Internal reference voltage  
spread over the temperature  
range  
(2)  
VRERINT  
VDD = 3 V 10 mV  
10  
mV  
(2)  
TCoeff  
Temperature coefficient  
100 ppm/°C  
1. Shortest sampling time can be determined in the application by multiple iterations.  
2. Guaranteed by design, not tested in production.  
5.3.5  
Supply current characteristics  
The current consumption is a function of several parameters and factors such as the  
operating voltage, ambient temperature, I/O pin loading, device software configuration,  
operating frequencies, I/O pin switching rate, program location in memory and executed  
binary code.  
The current consumption is measured as described in Figure 8: Current consumption  
measurement scheme.  
All Run-mode current consumption measurements given in this section are performed with a  
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.  
Maximum current consumption  
The MCU is placed under the following conditions:  
G
G
G
All I/O pins are in input mode with a static value at V or V (no load)  
DD SS  
All peripherals are disabled except when explicitly mentioned  
The Flash memory access time is adjusted to the f frequency (0 wait state from 0  
HCLK  
to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above)  
G
G
Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)  
When the peripherals are enabled f  
= f  
/2, f = f  
PCLK2 HCLK  
PCLK1  
HCLK  
The parameters given in Table 13, Table 14 and Table 15 are derived from tests performed  
under ambient temperature and V supply voltage conditions summarized in Table 9.  
DD  
36/95  
Doc ID 15274 Rev 4  
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