Electrical characteristics
STM32F103x8, STM32F103xB
5.3.12
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in
are derived from tests
performed under the conditions summarized in
All I/Os are CMOS and TTL
compliant.
Table 34.
Symbol
I/O static characteristics
Parameter
Standard I/O input low level
voltage
I/O FT
(1)
input low level voltage
Standard I/O input high level
voltage
I/O FT
(1)
input high level voltage
Standard IO Schmitt trigger
voltage hysteresis
(2)
Conditions
Min
–0.5
–0.5
0.41 (V
DD
–2)+1.3
0.42 (V
DD
–2)+1
200
5% V
DD(3)
V
SS
V
IN
V
DD
Standard I/Os
V
IN
= 5 V
I/O FT
Weak pull-up equivalent
resistor
(5)
Weak pull-down equivalent
resistor
I/O pin capacitance
V
IN
�½
V
SS
V
IN
�½
V
DD
30
30
40
40
5
1
µA
3
50
50
k
k
pF
Typ
Max
0.28 (V
DD
–2)+0.8
0.32 (V
DD
–2)+0.75
V
DD
+0.5
5.5
mV
mV
V
Unit
V
IL
V
IH
V
hys
IO FT Schmitt trigger voltage
hysteresis
(2)
I
lkg
Input leakage current
(4)
R
PU
R
PD
C
IO
1. FT = 5V tolerant. To sustain a voltage higher than V
DD
+0.5 the internal pull-up/pull-down resistors must be disabled.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution
to the series resistance is minimum
(~10% order)
.
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in
and
for standard I/Os, and
in
and
for 5 V tolerant I/Os.
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