Pinouts and pin description
STM32F405xx, STM32F407xx
Table 7. STM32F40x pin and ball definitions (continued)
Pin number
Pin name
Alternate functions
Additional functions
(function after
reset)(1)
USART2_RX/TIM5_CH4 /
TIM9_CH2 / TIM2_CH4 /
OTG_HS_ULPI_D0 /
ETH_MII_COL/
(4)
17 H9 26 37 R2 47
PA3
I/O FT
ADC123_IN3
EVENTOUT
18 E5 27 38
D9
-
-
VSS
BYPASS_REG
VDD
S
L4 48
I
FT
19 E4 28 39 K4 49
20 J9 29 40 N4 50
S
SPI1_NSS / SPI3_NSS /
USART2_CK /
DCMI_HSYNC /
OTG_HS_SOF/ I2S3_WS/
EVENTOUT
ADC12_IN4
/DAC_OUT1
(4)
(4)
(4)
PA4
PA5
PA6
I/O TTa
I/O TTa
I/O FT
SPI1_SCK/
OTG_HS_ULPI_CK /
TIM2_CH1_ETR/
ADC12_IN5/DAC_OU
T2
21 G8 30 41 P4 51
TIM8_CH1N/ EVENTOUT
SPI1_MISO /
TIM8_BKIN/TIM13_CH1 /
DCMI_PIXCLK /
TIM3_CH1 / TIM1_BKIN/
EVENTOUT
22 H8 31 42 P3 52
ADC12_IN6
ADC12_IN7
SPI1_MOSI/ TIM8_CH1N
/ TIM14_CH1/TIM3_CH2/
ETH_MII_RX_DV /
TIM1_CH1N /
(4)
23 J8 32 43 R3 53
PA7
I/O FT
ETH_RMII_CRS_DV/
EVENTOUT
ETH_RMII_RX_D0 /
ETH_MII_RX_D0/
EVENTOUT
(4)
(4)
24
25
-
-
33 44 N5 54
34 45 P5 55
PC4
PC5
I/O FT
I/O FT
ADC12_IN14
ADC12_IN15
ETH_RMII_RX_D1 /
ETH_MII_RX_D1/
EVENTOUT
TIM3_CH3 / TIM8_CH2N/
OTG_HS_ULPI_D1/
(4)
26 G7 35 46 R5 56
PB0
I/O FT
ADC12_IN8
ETH_MII_RXD2 /
TIM1_CH2N/ EVENTOUT
48/185
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STMICROELECTRONICS [ ST ]
