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STM32F107VCT6TR 参数 Datasheet PDF下载

STM32F107VCT6TR图片预览
型号: STM32F107VCT6TR
PDF下载: 下载PDF文件 查看货源
内容描述: [Mainstream Connectivity line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, Ethernet MAC, CAN and USB 2.0 OTG]
分类和应用: 闪存
文件页数/大小: 103 页 / 1881 K
品牌: STMICROELECTRONICS [ ST ]
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Description  
STM32F105xx, STM32F107xx  
Any of the standard timers can be used to generate PWM outputs. Each of the timers has  
independent DMA request generations.  
Basic timers TIM6 and TIM7  
These timers are mainly used for DAC trigger generation. They can also be used as a  
generic 16-bit time base.  
Independent watchdog  
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is  
clocked from an independent 40 kHz internal RC and as it operates independently from the  
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog  
to reset the device when a problem occurs, or as a free running timer for application timeout  
management. It is hardware or software configurable through the option bytes. The counter  
can be frozen in debug mode.  
Window watchdog  
The window watchdog is based on a 7-bit downcounter that can be set as free running. It  
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the  
main clock. It has an early warning interrupt capability and the counter can be frozen in  
debug mode.  
SysTick timer  
This timer is dedicated to real-time operating systems, but could also be used as a standard  
down counter. It features:  
A 24-bit down counter  
Autoreload capability  
Maskable system interrupt generation when the counter reaches 0.  
Programmable clock source  
2.3.16  
2.3.17  
I²C bus  
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support  
standard and fast modes.  
They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A  
hardware CRC generation/verification is embedded.  
They can be served by DMA and they support SMBus 2.0/PMBus.  
Universal synchronous/asynchronous receiver transmitters (USARTs)  
The STM32F105xx and STM32F107xx connectivity line embeds three universal  
synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and  
two universal asynchronous receiver transmitters (UART4 and UART5).  
These five interfaces provide asynchronous communication, IrDA SIR ENDEC support,  
multiprocessor communication mode, single-wire half-duplex communication mode and  
have LIN Master/Slave capability.  
The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other  
available interfaces communicate at up to 2.25 Mbit/s.  
18/104  
Doc ID 15274 Rev 6  
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