Revision history
Table 65. Document revision history (continued)
STM32F105xx, STM32F107xx
Date
Revision
Changes
Section 2.3.8: Boot modes and Section 2.3.20: Ethernet MAC
interface with dedicated DMA and IEEE 1588 support updated.
Section 2.3.24: Remap capability added.
Figure 1: STM32F105xx and STM32F107xx connectivity line block
diagram and Figure 5: Memory map updated.
In Table 5: Pin definitions:
– I2S3_WS, I2S3_CK and I2S3_SD default alternate functions
added
– small changes in signal names
– Note 6 modified
– ETH_MII_PPS_OUT and ETH_RMII_PPS_OUT replaced by
ETH_PPS_OUT
– ETH_MII_MDIO and ETH_RMII_MDIO replaced by ETH_MDIO
– ETH_MII_MDC and ETH_RMII_MDC replaced by ETH_MDC
Figures: Typical current consumption in Run mode versus frequency
(at 3.6 V) - code with data processing running from RAM, peripherals
enabled and Typical current consumption in Run mode versus
frequency (at 3.6 V) - code with data processing running from RAM,
peripherals disabled removed.
Table 13: Maximum current consumption in Run mode, code with
data processing running from Flash, Table 14: Maximum current
consumption in Run mode, code with data processing running from
RAM and Table 15: Maximum current consumption in Sleep mode,
code running from Flash or RAM are to be determined.
Figure 12 and Figure 13 show typical curves. PLL1 renamed to PLL.
IDD supply current in Stop mode modified in Table 16: Typical and
maximum current consumptions in Stop and Standby modes.
Figure 11: Typical current consumption in Stop mode with regulator
in Run mode versus temperature at different VDD values, Figure 13:
Typical current consumption in Standby mode versus temperature at
different VDD values and Figure 13: Typical current consumption in
Standby mode versus temperature at different VDD values updated.
Table 17: Typical current consumption in Run mode, code with data
processing running from Flash, Table 18: Typical current
consumption in Sleep mode, code running from Flash or RAM and
Table 19: Peripheral current consumption updated.
19-Jun-2009
3
fHSE_ext modified in Table 20: High-speed external user clock
characteristics.
Min PLL input clock (fPLL_IN), fPLL_OUT min and fPLL_VCO min
modified in Table 27: PLL characteristics.
ACCHSI max values modified in Table 24: HSI oscillator
characteristics. Table 31: EMS characteristics and Table 32: EMI
characteristics updated. Table 43: SPI characteristics updated.
Modified: Figure 28: I2S slave timing diagram (Philips protocol)(1),
Figure 29: I2S master timing diagram (Philips protocol)(1) and
Figure 31: Ethernet SMI timing diagram.
BGA100 package removed.
Section 6.2: Thermal characteristics added. Small text changes.
100/104
Doc ID 15274 Rev 6
STMICROELECTRONICS [ ST ]
