STM32F103xC, STM32F103xD, STM32F103xE
Table 63. DAC characteristics (continued)
Electrical characteristics
Comments
Symbol
Parameter
Min
Typ
Max
Unit
Given for the DAC in 12-bit
configuration
10
3
mV
Offset error
(difference between
measured value at Code
(0x800) and the ideal value =
VREF+/2)
Given for the DAC in 10-bit at VREF+
= 3.6 V
Offset(2)
LSB
LSB
%
Given for the DAC in 12-bit at VREF+
= 3.6 V
12
0.5
Gain
Given for the DAC in 12bit
configuration
Gain error
error(2)
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value 1LSB
(2)
tSETTLING
3
4
1
µs
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
Max frequency for a correct
DAC_OUT change when
small variation in the input
code (from code i to i+1LSB)
Update
rate(2)
MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
Wakeup time from off state
(Setting the ENx bit in the
DAC Control register)
(2)
tWAKEUP
6.5
10
µs
input code between lowest and
highest possible ones.
Power supply rejection ratio
PSRR+ (1) (to VDDA) (static DC
measurement
–67
–40
dB No RLOAD, CLOAD = 50 pF
1. Guaranteed by design, not tested in production.
2. Guaranteed by characterization, not tested in production.
Figure 61. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
R
LOAD
DACx_OUT
12-bit
digital to
analog
converter
C
LOAD
ai17157
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
Doc ID 14611 Rev 8
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STMICROELECTRONICS [ ST ]
