Electrical characteristics
STM32F103xx
Figure 23. ADC accuracy characteristics
EG
(1) Example of an actual transfer curve
1023
1022
1021
(2) The ideal transfer curve
(3) End point correlation line
V
– V
DDA
SSA
1LSB
= ----------------------------------------
IDEAL
1024
(2)
ET=Total Unadjusted Error: maximum deviation
ET
between the actual and the ideal transfer curves.
(3)
7
6
5
4
3
2
1
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
(1)
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
EO
EL
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
ED
1 LSBIDEAL
0
1
2
3
4
5
6
7
1021 1022 1023 1024
VDDA
VSSA
ai14395
Figure 24. Typical connection diagram using the ADC
V
DD
STM32F103xx
V
T
0.6V
R
R
AIN
ADC
AINx
(1)
12-bit A/D
conversion
V
T
I ±1mA
V
C
C
L
AIN
0.6V
AIN
ADC
ai14150
1. Refer to Table 39 for the values of RADC and CADC
.
2. CPARASITIC must be added to CAIN. It represents the capacitance of the PCB (dependent on soldering and
PCB layout quality) plus the pad capacitance (3 pF). A high CPARASITIC value will downgrade conversion
accuracy. To remedy this, fADC should be reduced.
56/67
STMICROELECTRONICS [ ST ]
