STA335BW
Register description
5.6.3
Binary output mode clock loss detection
Bit
R/W
RST
Name
Description
Binary output mode clock loss detection enable
3
R/W
1
BCLE
Detects loss of input MCLK in binary mode and will output 50% duty cycle.
5.6.4
5.6.5
5.6.6
LRCK double trigger protection
Bit
R/W
RST
Name
Description
4
R/W
1
LDTE
LRCLK double trigger protection enable
Actively prevents double trigger of LRCLK.
Auto EAPD on clock loss
Bit
R/W
RST
Name
Description
5
R/W
0
ECLE
Auto EAPD on clock loss
When active, issues a power device power down signal (EAPD) on clock loss detection.
IC power down
Bit
R/W
RST
Name
Description
0 - IC power down low-power condition
1 - IC normal operation
7
R/W
1
PWDN
The PWDN register is used to place the IC in a low-power state. When PWDN is written
as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted
to power down the power-stage, then the master clock to all internal hardware expect the
2
I C block is gated. This places the IC in a very low power consumption state.
5.6.7
External amplifier power down
Bit
R/W
RST
Name
Description
0 – External power stage power down active
1 – Normal operation
7
R/W
0
EAPD
The EAPD register directly disables/enables the internal power circuitry.
When EAPD = 0, the internal power section is placed on a low-power state (disabled). This
register also controls the DDX4B/EAPD output pin when OCFG = 10.
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STMICROELECTRONICS [ ST ]
