ST92F124/F150/F250 - DEVICE ARCHITECTURE
MMU REGISTERS (Cont’d)
DATA PAGE REGISTER 0 (DPR0)
R240 - Read/Write
DATA PAGE REGISTER 2 (DPR2)
R242 - Read/Write
Register Page: 21
Register Page: 21
Reset value: undefined
Reset value: undefined
This register is relocated to R224 if EMR2.5 is set.
This register is relocated to R226 if EMR2.5 is set.
7
0
7
0
DPR0 DPR0 DPR0 DPR0 DPR0 DPR0 DPR0 DPR0
_7 _6 _5 _4 _3 _2 _1 _0
DPR2 DPR2 DPR2 DPR2 DPR2 DPR2 DPR2 DPR2
_7 _6 _5 _4 _3 _2 _1 _0
Bits 7:0 = DPR0_[7:0]: These bits define the 16-
Kbyte Data Memory page number. They are used
as the most significant address bits (A21-14) to ex-
tend the address during a Data Memory access.
The DPR0 register is used when addressing the
virtual address range 0000h-3FFFh.
Bits 7:0 = DPR2_[7:0]: These bits define the 16-
Kbyte Data memory page. They are used as the
most significant address bits (A21-14) to extend
the address during a Data memory access. The
DPR2 register is involved when the virtual address
is in the range 8000h-BFFFh.
DATA PAGE REGISTER 1 (DPR1)
R241 - Read/Write
DATA PAGE REGISTER 3 (DPR3)
R243 - Read/Write
Register Page: 21
Register Page: 21
Reset value: undefined
Reset value: undefined
This register is relocated to R225 if EMR2.5 is set.
This register is relocated to R227 if EMR2.5 is set.
7
0
7
0
DPR1 DPR1 DPR1 DPR1 DPR1 DPR1 DPR1 DPR1
_7 _6 _5 _4 _3 _2 _1 _0
DPR3 DPR3 DPR3 DPR3 DPR3 DPR3 DPR3 DPR3
_7 _6 _5 _4 _3 _2 _1 _0
Bits 7:0 = DPR1_[7:0]: These bits define the 16-
Kbyte Data Memory page number. They are used
as the most significant address bits (A21-14) to ex-
tend the address during a Data Memory access.
The DPR1 register is used when addressing the
virtual address range 4000h-7FFFh.
Bits 7:0 = DPR3_[7:0]: These bits define the 16-
Kbyte Data memory page. They are used as the
most significant address bits (A21-14) to extend
the address during a Data memory access. The
DPR3 register is involved when the virtual address
is in the range C000h-FFFFh.
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STMICROELECTRONICS [ ST ]
