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ST92F150JDV1Q6 参数 Datasheet PDF下载

ST92F150JDV1Q6图片预览
型号: ST92F150JDV1Q6
PDF下载: 下载PDF文件 查看货源
内容描述: 8月16日- BIT单电压闪存单片机系列内存, E3 TMEMULATED EEPROM , CAN 2.0B和J1850 BLPD [8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TMEMULATED EEPROM, CAN 2.0B AND J1850 BLPD]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 426 页 / 3830 K
品牌: STMICROELECTRONICS [ ST ]
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MULTIFUNCTION TIMER (MFT)  
MULTIFUNCTION TIMER (Cont’d)  
10.4.5.6 DMA End Of Block Interrupt Routine  
– Return.  
WARNING: The EOB bits are read/write only for  
test purposes. Writing a logical “1” by software  
(when the SWEN bit is set) will cause a spurious  
interrupt request. These bits are normally only re-  
set by software.  
An interrupt request is generated after each block  
transfer (EOB) and its priority is the same as that  
assigned in the usual interrupt request, for the two  
channels. As a consequence, they will be serviced  
only when no DMA request occurs, and will be  
subject to a possible OUF Interrupt request, which  
has higher priority.  
10.4.5.7 DMA Software Protection  
A second EOB condition may occur before the first  
EOB routine is completed, this would cause a not  
yet updated pointer pair to be addressed, with con-  
sequent overwriting of memory. To prevent these  
errors, a protection mechanism is provided, such  
that the attempted setting of the EOB bit before it  
has been reset by software will cause the DMA  
mask on that channel to be reset (DMA disabled),  
thus blocking any further DMA operation. As  
shown above, this mask bit should always be  
checked in each EOB routine, to ensure that all  
DMA transfers are properly served.  
The following is a typical EOB procedure (with  
swap mode enabled):  
– Test Toggle bit and Jump.  
– Reload Pointers (odd or even depending on tog-  
gle bit status).  
– Reset EOB bit: this bit must be reset only after  
the old pair of pointers has been restored, so  
that, if a new EOB condition occurs, the next pair  
of pointers is ready for swapping.  
– Verify the software protection condition (see  
Section 10.4.5.7).  
10.4.6 Register Description  
– Read the corresponding Overrun bit: this con-  
firms that no DMA request has been lost in the  
meantime.  
Note: In the register description on the following  
pages, register and page numbers are given using  
the example of Timer 0. On devices with more  
than one timer, refer to the device register map for  
the adresses and page numbers.  
– Reset the corresponding pending bit.  
– Reenable DMA with the corresponding DMA  
mask bit (must always be done after resetting  
the pending bit)  
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