MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
10.4.2.8 Free Running Mode
The Clear On Capture mode allows direct meas-
urement of delta time between successive cap-
tures on REG0R, while the Clear On Compare
mode allows free running with the possibility of
choosing a maximum count value before overflow
The timer counts continuously (in Up or Down
mode) and the counter value simply overflows or
underflows through FFFFh or zero; there is no End
Of Count condition as such, and no reloading
takes place. This mode is automatically selected
either in Bi-capture mode or by setting register
REG0R for a Capture function (Continuous mode
must also be set). In Autoclear mode, free running
operation can be selected, with the possibility of
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or underflow which is less than 2 (see Free Run-
ning Mode).
10.4.2.11 Bi-value Mode
Depending on the value of the RM0 bit in TMR, the
Bi-load Mode (RM0 reset) or the Bi-capture Mode
(RM0 set) can be selected as illustrated in Figure
38 below:
16
choosing a maximum count value less than 2
before overflow or underflow (see Autoclear
mode).
Table 38. Bi-value Modes
10.4.2.9 Monitor Mode
When the RM1 bit in TMR is reset, and the timer is
not in Bi-value mode, REG1R acts as a monitor,
duplicating the current up or down counter con-
tents, thus allowing the counter to be read “on the
fly”.
TMR bits
RM1
Timer
Operating Modes
RM0
0
1
BM
1
1
X
X
Bi-Load mode
Bi-Capture Mode
10.4.2.10 Autoclear Mode
A) Biload Mode
A clear command forces the counter either to
0000h or to FFFFh, depending on whether up-
counting or downcounting is selected. The counter
reset may be obtained either directly, through the
CCL bit in TCR, or by entering the Autoclear
Mode, through the CCP0 and CCMP0 bits in TCR.
The Bi-load Mode is entered by selecting the Bi-
value Mode (BM set in TMR) and programming
REG0R as a reload register (RM0 reset in TMR).
At any End Of Count, counter reloading is per-
formed alternately from REG0R and REG1R, (a
low level for BM bit always sets REG0R as the cur-
rent register, so that, after a Low to High transition
of BM bit, the first reload is always from REG0R).
Every capture performed on REG0R (if CCP0 is
set), or every successful compare performed by
CMP0R (if CCMP0 is set), clears the counter and
reloads the prescaler.
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STMICROELECTRONICS [ ST ]
