ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
RESET/STOP MANAGER (Cont’d)
The on-chip Timer/Watchdog generates a reset
condition if the Watchdog mode is enabled
(WCR.WDGEN cleared, R252 page 0), and if the
programmed period elapses without the specific
code (AAh, 55h) written to the appropriate register.
The input pin RESET is not driven low by the on-
chip reset generated by the Timer/Watchdog.
of up to 4µs will elapse before the RCCU detects
this rising front. From this event on, a defined
number of CLOCK1 cycles (refer to t ) is
counted before exiting the Reset state (+ one pos-
sible CLOCK1 period depending on the delay be-
tween the positive edge the RCCU detects and the
first rising edge of CLOCK1).
If the ST9 is a ROMLESS version, without on-chip
program memory, the memory interface ports are
set to external memory mode (i.e Alternate Func-
tion) and the memory accesses are made to exter-
nal Program memory with wait cycles insertion.
If the Voltage Regulator is present in the device,
please ensure the reset pin is released only when
the internal voltage supply is stabilized at 3.3V.
RSPH
When the Reset pin goes high again, 20479 oscil-
lator clock cycles (CLOCK1) are counted before ex-
iting the Reset state (+ one possible CLOCK1 pe-
riod, depending on the delay between the rising
edge of the Reset pin and the first rising edge of
CLOCK1). Subsequently a short Boot routine is ex-
ecuted from the device internal Boot memory, and
control then passes to the user program.
The Boot routine sets the device characteristics
and loads the correct values in the Memory Man-
agement Unit’s pointer registers, so that these
point to the physical memory areas as mapped in
the specific device. The precise duration of this
short Boot routine varies from device to device,
depending on the Boot memory contents.
Figure 71. Recommended Signal to be Applied
on Reset Pin
V
RESETN
V
DD
At the end of the Boot routine the Program Coun-
ter will be set to the location specified in the Reset
Vector located in the lowest two bytes of memory.
V
IHRS
V
ILRS
7.6.1 Reset Pin Timing
To improve the noise immunity of the device, the
Reset pin has a Schmitt trigger input circuit with
hysteresis. In addition, a filter will prevent an un-
wanted reset in case of a single glitch of less than
50 ns on the Reset pin. The device is certain to re-
set if a negative pulse of more than 20µs is ap-
plied. When the reset pin goes high again, a delay
20µs
Minimum
Figure 72. Reset Pin Input Structure
PIN
SCHMITT TRIGGER and LOW
PASS FILTER
TO GENERATE RESET SIGNAL
E
SD PROTECTION
CIRCUITRY
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STMICROELECTRONICS [ ST ]
