ST24E16, ST25E16
Figure 8. Write Modes Sequence with Write Control = 0
WC
ACK
ACK
ACK
NO ACK
DATA IN
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
R/W
WC
ACK
ACK
ACK
NO ACK
DATA IN 1 DATA IN 2
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
R/W
WC (cont'd)
NO ACK
NO ACK
PAGE WRITE
(cont'd)
DATA IN N
AI01120B
Read Operations
Random Address Read. A dummy write is per-
formed to load the address into the address
counter, see Figure 10. This is followed by another
START condition from the master and the byte
address repeated with the RW bit set to ’1’. The
ST24/25E16 acknowledge this and outputs the
byte addressed. The master does NOT acknow-
ledge the byte output, but terminates the transfer
with a STOP condition.
Sequential Read. This mode can be initiated with
either a Current Address Read or a Random Ad-
dress Read. However, in this case the master
DOES acknowledge the data byte output and the
ST24/25E16 continue to output the next byte in
On delivery, the memory content is set at all "1’s"
(or FFh).
Current Address Read. The ST24/25E16 have
an internal 11 bits address counter. Each time a
byte is read, this counter is incremented. For the
Current Address Read mode, following a START
condition, the master sends a Device Select with
the RWbit setto ’1’. The ST24/25E16acknowledge
this and outputs the byte addressed by the internal
address counter. This counter is then incremented.
The master does NOT acknowledge the byte out-
put, but terminates the transfer with a STOP con-
dition.
10/16
STMICROELECTRONICS [ ST ]
