ST24/25C16, ST24/25W16
Table 7. AC Characteristics
(T
A
= 0 to 70
°C
or –40 to 85
°C;
V
CC
= 4.5V to 5.5V or 2.5V to 5.5V)
Symbol
t
CH1CH2
t
CL1CL2
t
DH1DH2
t
DL1DL1
t
CHDX (1)
t
CHCL
t
DLCL
t
CLDX
t
CLCH
t
DXCX
t
CHDH
t
DHDL
t
CLQV (2)
t
CLQX
f
C
t
W (3)
Alt
t
R
t
F
t
R
t
F
t
SU:STA
t
HIGH
t
HD:STA
t
HD:DAT
t
LOW
t
SU:DAT
t
SU:STO
t
BUF
t
AA
t
DH
f
SCL
t
WR
Clock Rise Time
Clock Fall Time
Input Rise Time
Input Fall Time
Clock High to Input Transition
Clock Pulse Width High
Input Low to Clock Low (START)
Clock Low to Input Transition
Clock Pulse Width Low
Input Transition to Clock Transition
Clock High to Input High (STOP)
Input High to Input Low (Bus Free)
Clock Low to Next Data Out Valid
Data Out Hold Time
Clock Frequency
Write Time
4.7
4
4
0
4.7
250
4.7
4.7
0.3
300
100
10
3.5
Parameter
Min
Max
1
300
1
300
Unit
µs
ns
µs
ns
µs
µs
µs
µs
µs
ns
µs
µs
µs
ns
kHz
ms
Notes:
1. For a reSTART condition, or following a write cycle.
2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.
3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (5 address MSB are not constant)
the maximum programming time is doubled to 20ms.
Table 8. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref.
Voltages
≤
50ns
0.2V
CC
to 0.8V
CC
0.3V
CC
to 0.7V
CC
Figure 4. AC Testing Input Output Waveforms
0.8VCC
0.7VCC
0.3VCC
AI00825
0.2VCC
DEVICE OPERATION
I
2
C Bus Background
The ST24/25x16 support the I
2
C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the
data transfer is known as the master and the other
as the slave. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The ST24/25x16 are always slave
devices in all communications.
Start Condition.
START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25x16 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
6/17
STMICROELECTRONICS [ STMICROELECTRONICS ]
