ST24/25C16, ST24/25W16
Table 3. Device Select Code
Device Code
Bit
Device Select
Note:
The MSB b7 is sent first.
Memory MSB Addresses
b4
0
b3
A10
b2
A9
b1
A8
RW
b0
RW
b7
1
b6
0
b5
1
Table 4. Operating Modes
Mode
Current Address Read
Random Address Read
Sequential Read
Byte Write
Multibyte Write
Page Write
Note:
X = V
IH
or V
IL
.
RW bit
’1’
’0’
’1’
’1’
’0’
’0’
’0’
MODE pin
X
X
X
X
V
IH
V
IL
Bytes
1
1
1 to 2048
1
8
16
Initial Sequence
START, Device Select, RW = ’1’
START, Device Select, RW = ’0’, Address,
reSTART, Device Select, RW = ’1’
As CURRENT or RANDOM Mode
START, Device Select, RW = ’0’
START, Device Select, RW = ’0’
START, Device Select, RW = ’0’
memory it responds to the 8 bits received by as-
serting an acknowledge bit during the 9th bit time.
When data is read by the bus master, it acknow-
ledges the receipt of the data bytes in the same
way. Data transfers are terminated with a STOP
condition.
Data in the 4 upper blocks of the memory may be
write protected. The protected area is programma-
ble to start on any 16 byte boundary. The block in
which the protection starts is selected by the input
pins PB0, PB1. Protection is enabled by setting a
Protect Flag bit when the PRE input pin is driven
High.
Power On Reset: V
CC
lock out write protect.
In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Untill the V
CC
voltage has reached the POR threshold value, the
internal reset is active: all operations are disabled
and the device will not respond to any command.
In the same way, when V
CC
drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable V
CC
must be applied before applying any logic signal.
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STMICROELECTRONICS [ STMICROELECTRONICS ]
