Bootstrap loader
ST10F276E
5.2.2
ST10 configuration in BSL
When the ST10F276E has entered BSL mode, the configuration shown in Table 29 is
automatically set (values that deviate from the normal reset values are marked in bold).
Table 29. ST10 configuration in BSL mode
Function or register
Access
Disabled
Notes
Watchdog Timer
XPEN bit set for Bootstrap via CAN or
Alternate Boot Mode
(1)
Register SYSCON
0404H
Context Pointer CP
Register STKUN
Stack Pointer SP
Register STKOV
Register BUSCON0
Register S0CON
Register S0BG
P3.10 / TXD0
FA00H
FC00H
FA40H
FA00H
acc. to startup config.(2)
8011H
Initialized only if Bootstrap via UART
Initialized only if Bootstrap via UART
Initialized only if Bootstrap via UART
Initialized only if Bootstrap via UART
acc. to ‘00’ byte
‘1’
‘1’
DP3.10
CAN1 Status/Control
Register
0000H
Initialized only if Bootstrap via CAN
Initialized only if Bootstrap via CAN
CAN1 Bit Timing Register acc. to ‘0’ frame
XRAM1-2, XFlash, CAN1 and XMISC
enabled. Initialized only if Bootstrap via CAN
XPERCON
042DH
P4.6 / CAN1_TxD
DP4.6
‘1’
‘1’
Initialized only if Bootstrap via CAN
Initialized only if Bootstrap via CAN
1. In Bootstrap modes (standard or alternate) ROMEN, bit 10 of SYSCON, is always set regardless of EA pin
level. BYTDIS, bit 9 of SYSCON, is set according to data bus width selection via Port0 configuration.
2. BUSCON0 is initialized with 0000h, external bus disabled, if pin EA is high during reset. If pin EA is low
during reset, BUSACT0, bit 10, and ALECTL0, bit 9, are set enabling the external bus with lengthened ALE
signal. BTYP field, bit 7 and 6, is set according to Port0 configuration.
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Doc ID 12303 Rev 3
STMICROELECTRONICS [ ST ]
